aarch64_cpu/registers/
mpidr_el1.rs

1// SPDX-License-Identifier: Apache-2.0 OR MIT
2//
3// Copyright (c) 2018-2023 by the author(s)
4//
5// Author(s):
6//   - Andre Richter <andre.o.richter@gmail.com>
7
8//! Multiprocessor Affinity Register - EL1
9//!
10//! In a multiprocessor system, provides an additional PE identification mechanism for scheduling
11//! purposes.
12
13use tock_registers::{interfaces::Readable, register_bitfields};
14
15register_bitfields! {u64,
16    pub MPIDR_EL1 [
17        /// Affinity level 3. See the description of Aff0 for more information.
18        Aff3 OFFSET(32) NUMBITS(8) [],
19
20        /// Reserved, RES1.
21        RES1 OFFSET(31) NUMBITS(1) [],
22
23        /// Indicates a Uniprocessor system, as distinct from PE 0 in a multiprocessor system.
24        U OFFSET(30) NUMBITS(1) [
25            MultiprocessorSystem = 0b0,
26            UniprocessorSystem = 0b1,
27        ],
28
29        /// Indicates whether the lowest level of affinity consists of logical PEs that are implemented using a
30        /// multithreading type approach. See the description of Aff0 for more information about affinity levels
31        MT OFFSET(24) NUMBITS(1) [],
32
33        /// Affinity level 2. See the description of Aff0 for more information.
34        Aff2 OFFSET(16) NUMBITS(8) [],
35
36        /// Affinity level 1. See the description of Aff0 for more information.
37        Aff1 OFFSET(8) NUMBITS(8) [],
38
39        /// Affinity level 0.  This is the affinity level that is most significant for determining PE behavior.  Higher
40        /// affinity levels are increasingly less significant in determining PE behavior.
41        Aff0 OFFSET(0) NUMBITS(8) []
42    ]
43}
44
45pub struct Reg;
46
47impl Readable for Reg {
48    type T = u64;
49    type R = MPIDR_EL1::Register;
50
51    sys_coproc_read_raw!(u64, "MPIDR_EL1", "x");
52}
53
54pub const MPIDR_EL1: Reg = Reg {};
aarch64_cpu/registers/mpidr_el1.rs

aarch64_cpu/registers/
mpidr_el1.rs
