aarch64_cpu/registers/
id_aa64mmfr0_el1.rs

1// SPDX-License-Identifier: Apache-2.0 OR MIT
2//
3// Copyright (c) 2018-2023 by the author(s)
4//
5// Author(s):
6//   - Andre Richter <andre.o.richter@gmail.com>
7
8//! AArch64 Memory Model Feature Register 0 - EL1
9//!
10//! Provides information about the implemented memory model and memory
11//! management support in AArch64 state.
12
13use tock_registers::{interfaces::Readable, register_bitfields};
14
15register_bitfields! {u64,
16    pub ID_AA64MMFR0_EL1 [
17        /// Support for 4KiB memory translation granule size. Defined values are:
18        ///
19        /// 0000 4KiB granule supported.
20        /// 1111 4KiB granule not supported.
21        ///
22        /// All other values are reserved.
23        TGran4  OFFSET(28) NUMBITS(4) [
24            Supported = 0b0000,
25            NotSupported = 0b1111
26        ],
27
28        /// Support for 64KiB memory translation granule size. Defined values are:
29        ///
30        /// 0000 64KiB granule supported.
31        /// 1111 64KiB granule not supported.
32        ///
33        /// All other values are reserved.
34        TGran64 OFFSET(24) NUMBITS(4) [
35            Supported = 0b0000,
36            NotSupported = 0b1111
37        ],
38
39        /// Support for 16KiB memory translation granule size. Defined values are:
40        ///
41        /// 0001 16KiB granule supported.
42        /// 0000 16KiB granule not supported.
43        ///
44        /// All other values are reserved.
45        TGran16 OFFSET(20) NUMBITS(4) [
46            Supported = 0b0001,
47            NotSupported = 0b0000
48        ],
49
50        /// Number of bits supported in the ASID:
51        ///
52        /// 0000 ASIDs are 8 bits.
53        /// 0010 ASIDs are 16 bits.
54        ///
55        /// All other values are reserved.
56        ASIDBits OFFSET(4) NUMBITS(4) [
57            Bits_8 = 0b0000,
58            Bits_16 = 0b0010
59        ],
60
61        /// Physical Address range supported. Defined values are:
62        ///
63        /// 0000 32 bits, 4GiB.
64        /// 0001 36 bits, 64GiB.
65        /// 0010 40 bits, 1TiB.
66        /// 0011 42 bits, 4TiB.
67        /// 0100 44 bits, 16TiB.
68        /// 0101 48 bits, 256TiB.
69        /// 0110 52 bits, 4PiB.
70        ///
71        /// All other values are reserved.
72        ///
73        /// The value 0110 is permitted only if the implementation includes ARMv8.2-LPA, otherwise
74        /// it is reserved.
75        PARange OFFSET(0) NUMBITS(4) [
76            Bits_32 = 0b0000,
77            Bits_36 = 0b0001,
78            Bits_40 = 0b0010,
79            Bits_42 = 0b0011,
80            Bits_44 = 0b0100,
81            Bits_48 = 0b0101,
82            Bits_52 = 0b0110
83        ]
84    ]
85}
86
87pub struct Reg;
88
89impl Readable for Reg {
90    type T = u64;
91    type R = ID_AA64MMFR0_EL1::Register;
92
93    sys_coproc_read_raw!(u64, "ID_AA64MMFR0_EL1", "x");
94}
95
96pub const ID_AA64MMFR0_EL1: Reg = Reg {};
aarch64_cpu/registers/id_aa64mmfr0_el1.rs

aarch64_cpu/registers/
id_aa64mmfr0_el1.rs
