aarch64_cpu/registers/
id_aa64isar0_el1.rs

1// SPDX-License-Identifier: Apache-2.0 OR MIT
2//
3// Copyright (c) 2022-2023 Amazon.com, Inc. or its affiliates.
4//
5// Author(s):
6//   - Ali Saidi <alisaidi@amazon.com>
7
8//! AArch64 Instruction Set Architecture Feature Register 0 - EL1
9//!
10//! Provides information about the implemented instruction set.
11
12use tock_registers::{interfaces::Readable, register_bitfields};
13
14register_bitfields! {u64,
15    pub ID_AA64ISAR0_EL1 [
16        /// Support for Random Number instructions in AArch64.
17        ///
18        /// 0000 No random number instructions are implemented
19        /// 0001 RNDR and RNDRSS are implemented
20        ///
21        /// All other values are reserved.
22        RNDR OFFSET(60) NUMBITS(4) [
23            Supported = 0b0001,
24            NotSupported = 0b0000
25        ],
26    ]
27}
28
29pub struct Reg;
30
31impl Readable for Reg {
32    type T = u64;
33    type R = ID_AA64ISAR0_EL1::Register;
34
35    sys_coproc_read_raw!(u64, "ID_AA64ISAR0_EL1", "x");
36}
37
38pub const ID_AA64ISAR0_EL1: Reg = Reg {};