aarch64_cpu/registers/
esr_el2.rs

1// SPDX-License-Identifier: Apache-2.0 OR MIT
2//
3// Copyright (c) 2018-2023 by the author(s)
4//
5// Author(s):
6//   - Andre Richter <andre.o.richter@gmail.com>
7//   - Berkus Decker <berkus+github@metta.systems>
8//   - Bradley Landherr <landhb@users.noreply.github.com>
9
10//! Exception Syndrome Register - EL2
11//!
12//! Holds syndrome information for an exception taken to EL2.
13
14use tock_registers::{
15    interfaces::{Readable, Writeable},
16    register_bitfields,
17};
18
19register_bitfields! {u64,
20    pub ESR_EL2 [
21
22        /// Reserved
23        RES0 OFFSET(37) NUMBITS(27) [],
24
25        /// Instruction Specific Syndrome 2. If a memory access generated by an ST64BV or ST64BV0
26        /// instruction generates a Data Abort for a Translation fault, Access flag fault, or
27        /// Permission fault, then this field holds register specifier, Xs.
28        ///
29        /// For any other Data Abort, this field is RES0.
30        ISS2 OFFSET(32) NUMBITS(5) [],
31
32        /// Exception Class. Indicates the reason for the exception that this register holds
33        /// information about.
34        ///
35        /// For each EC value, the table references a subsection that gives information about:
36        ///   - The cause of the exception, for example the configuration required to enable the
37        ///     trap.
38        ///   - The encoding of the associated ISS.
39        ///
40        /// Incomplete listing - to be done.
41        EC  OFFSET(26) NUMBITS(6) [
42            Unknown               = 0b00_0000,
43            TrappedWFIorWFE       = 0b00_0001,
44            TrappedMCRorMRC       = 0b00_0011, // A32
45            TrappedMCRRorMRRC     = 0b00_0100, // A32
46            TrappedMCRorMRC2      = 0b00_0101, // A32
47            TrappedLDCorSTC       = 0b00_0110, // A32
48            TrappedFP             = 0b00_0111,
49            TrappedMRRC           = 0b00_1100, // A32
50            BranchTarget          = 0b00_1101,
51            IllegalExecutionState = 0b00_1110,
52            SVC32                 = 0b01_0001, // A32
53            SVC64                 = 0b01_0101,
54            HVC64                 = 0b01_0110,
55            SMC64                 = 0b01_0111,
56            TrappedMsrMrs         = 0b01_1000,
57            TrappedSve            = 0b01_1001,
58            PointerAuth           = 0b01_1100,
59            InstrAbortLowerEL     = 0b10_0000,
60            InstrAbortCurrentEL   = 0b10_0001,
61            PCAlignmentFault      = 0b10_0010,
62            DataAbortLowerEL      = 0b10_0100,
63            DataAbortCurrentEL    = 0b10_0101,
64            SPAlignmentFault      = 0b10_0110,
65            TrappedFP32           = 0b10_1000, // A32
66            TrappedFP64           = 0b10_1100,
67            SError                = 0b10_1111,
68            BreakpointLowerEL     = 0b11_0000,
69            BreakpointCurrentEL   = 0b11_0001,
70            SoftwareStepLowerEL   = 0b11_0010,
71            SoftwareStepCurrentEL = 0b11_0011,
72            WatchpointLowerEL     = 0b11_0100,
73            WatchpointCurrentEL   = 0b11_0101,
74            Bkpt32                = 0b11_1000, // A32 BKTP instruction
75            Brk64                 = 0b11_1100  // A64 BRK instruction
76        ],
77
78        /// Instruction Length for synchronous exceptions.
79        IL  OFFSET(25) NUMBITS(1) [],
80
81        /// Instruction Specific Syndrome. Architecturally, this field can be defined independently
82        /// for each defined Exception class. However, in practice, some ISS encodings are used for
83        /// more than one Exception class.
84        ISS OFFSET(0)  NUMBITS(25) []
85    ]
86}
87
88pub struct Reg;
89
90impl Readable for Reg {
91    type T = u64;
92    type R = ESR_EL2::Register;
93
94    sys_coproc_read_raw!(u64, "ESR_EL2", "x");
95}
96
97impl Writeable for Reg {
98    type T = u64;
99    type R = ();
100
101    sys_coproc_write_raw!(u64, "ESR_EL2", "x");
102}
103
104pub const ESR_EL2: Reg = Reg {};
aarch64_cpu/registers/esr_el2.rs

aarch64_cpu/registers/
esr_el2.rs
