aarch64_cpu/registers/
cntv_ctl_el0.rs

1// SPDX-License-Identifier: Apache-2.0 OR MIT
2//
3// Copyright (c) 2018-2023 by the author(s)
4//
5// Author(s):
6//   - Andre Richter <andre.o.richter@gmail.com>
7//   - Gregor Reitzenstein <me@dequbed.space>
8
9//! Counter-timer Virtual Timer Control register - EL0
10//!
11//! Control register for the virtual timer
12
13use tock_registers::{
14    interfaces::{Readable, Writeable},
15    register_bitfields,
16};
17
18register_bitfields! {u64,
19    pub CNTV_CTL_EL0 [
20        /// The status of the timer. This bit indicates whether the timer condition is met:
21        ///
22        /// 0 Timer condition is not met.
23        /// 1 Timer condition is met.
24        ///
25        /// When the value of the ENABLE bit is 1, ISTATUS indicates whether the timer condition is
26        /// met. ISTATUS takes no account of the value of the IMASK bit. If the value of ISTATUS is
27        /// 1 and the value of IMASK is 0 then the timer interrupt is asserted.
28        ///
29        /// When the value of the ENABLE bit is 0, the ISTATUS field is UNKNOWN.
30        ///
31        /// This bit is read-only.
32        ISTATUS OFFSET(2) NUMBITS(1) [],
33
34        /// Timer interrupt mask bit. Permitted values are:
35        ///
36        /// 0 Timer interrupt is not masked by the IMASK bit.
37        /// 1 Timer interrupt is masked by the IMASK bit.
38        IMASK   OFFSET(1) NUMBITS(1) [],
39
40        /// Enables the timer. Permitted values are:
41        ///
42        /// 0 Timer disabled.
43        /// 1 Timer enabled.
44        ///
45        /// Setting this bit to 0 disables the timer output signal but the timer value accessible
46        /// from `CNTV_TVAL_EL0` continues to count down.
47        ///
48        /// Disabling the output signal might be a power-saving option
49        ENABLE  OFFSET(0) NUMBITS(1) []
50    ]
51}
52
53pub struct Reg;
54
55impl Readable for Reg {
56    type T = u64;
57    type R = CNTV_CTL_EL0::Register;
58
59    sys_coproc_read_raw!(u64, "CNTV_CTL_EL0", "x");
60}
61
62impl Writeable for Reg {
63    type T = u64;
64    type R = CNTV_CTL_EL0::Register;
65
66    sys_coproc_write_raw!(u64, "CNTV_CTL_EL0", "x");
67}
68
69pub const CNTV_CTL_EL0: Reg = Reg {};
aarch64_cpu/registers/cntv_ctl_el0.rs

aarch64_cpu/registers/
cntv_ctl_el0.rs
