aarch64_cpu/registers/
cntp_cval_el0.rs

1// SPDX-License-Identifier: Apache-2.0 OR MIT
2//
3// Copyright (c) 2018-2023 by the author(s)
4//
5// Author(s):
6//   - Andre Richter <andre.o.richter@gmail.com>
7
8//! Counter-timer Physical Timer CompareValue register - EL0
9//!
10//! Holds the compare value for the EL1 physical timer.
11//!
12//! When CNTP_CTL_EL0.ENABLE is 1, the timer condition is met when (CNTPCT_EL0 - CompareValue) is
13//! greater than or equal to zero. This means that CompareValue acts like a 64-bit upcounter timer.
14//!
15//! When the timer condition is met:
16//!   - CNTP_CTL_EL0.ISTATUS is set to 1.
17//!   - If CNTP_CTL_EL0.IMASK is 0, an interrupt is generated.
18//!
19//! When CNTP_CTL_EL0.ENABLE is 0, the timer condition is not met, but CNTPCT_EL0 continues to
20//! count.
21//!
22//! If the Generic counter is implemented at a size less than 64 bits, then this field is permitted
23//! to be implemented at the same width as the counter, and the upper bits are RES0.
24//!
25//! The value of this field is treated as zero-extended in all counter calculations.
26//!
27//! The reset behaviour of this field is:
28//!   - On a Warm reset, this field resets to an architecturally UNKNOWN value.
29
30use tock_registers::interfaces::{Readable, Writeable};
31
32pub struct Reg;
33
34impl Readable for Reg {
35    type T = u64;
36    type R = ();
37
38    sys_coproc_read_raw!(u64, "CNTP_CVAL_EL0", "x");
39}
40
41impl Writeable for Reg {
42    type T = u64;
43    type R = ();
44
45    sys_coproc_write_raw!(u64, "CNTP_CVAL_EL0", "x");
46}
47
48pub const CNTP_CVAL_EL0: Reg = Reg {};
aarch64_cpu/registers/cntp_cval_el0.rs

aarch64_cpu/registers/
cntp_cval_el0.rs
