aarch64_cpu/registers/
cntp_ctl_el0.rs

1// SPDX-License-Identifier: Apache-2.0 OR MIT
2//
3// Copyright (c) 2018-2023 by the author(s)
4//
5// Author(s):
6//   - Andre Richter <andre.o.richter@gmail.com>
7
8//! Counter-timer Physical Timer Control register - EL0
9//!
10//! Control register for the EL1 physical timer.
11
12use tock_registers::{
13    interfaces::{Readable, Writeable},
14    register_bitfields,
15};
16
17register_bitfields! {u64,
18    pub CNTP_CTL_EL0 [
19        /// The status of the timer. This bit indicates whether the timer condition is met:
20        ///
21        /// 0 Timer condition is not met.
22        /// 1 Timer condition is met.
23        ///
24        /// When the value of the ENABLE bit is 1, ISTATUS indicates whether the timer condition is
25        /// met. ISTATUS takes no account of the value of the IMASK bit. If the value of ISTATUS is
26        /// 1 and the value of IMASK is 0 then the timer interrupt is asserted.
27        ///
28        /// When the value of the ENABLE bit is 0, the ISTATUS field is UNKNOWN.
29        ///
30        /// This bit is read-only.
31        ISTATUS OFFSET(2) NUMBITS(1) [],
32
33        /// Timer interrupt mask bit. Permitted values are:
34        ///
35        /// 0 Timer interrupt is not masked by the IMASK bit.
36        /// 1 Timer interrupt is masked by the IMASK bit.
37        IMASK   OFFSET(1) NUMBITS(1) [],
38
39        /// Enables the timer. Permitted values are:
40        ///
41        /// 0 Timer disabled.
42        /// 1 Timer enabled.
43        ENABLE  OFFSET(0) NUMBITS(1) []
44    ]
45}
46
47pub struct Reg;
48
49impl Readable for Reg {
50    type T = u64;
51    type R = CNTP_CTL_EL0::Register;
52
53    sys_coproc_read_raw!(u64, "CNTP_CTL_EL0", "x");
54}
55
56impl Writeable for Reg {
57    type T = u64;
58    type R = CNTP_CTL_EL0::Register;
59
60    sys_coproc_write_raw!(u64, "CNTP_CTL_EL0", "x");
61}
62
63pub const CNTP_CTL_EL0: Reg = Reg {};
aarch64_cpu/registers/cntp_ctl_el0.rs

aarch64_cpu/registers/
cntp_ctl_el0.rs
