aarch64_cpu/registers/clidr_el1.rs
1// SPDX-License-Identifier: Apache-2.0 OR MIT
2//
3// Copyright (c) 2018-2023 by the author(s)
4//
5// Author(s):
6// - Valentin B. <valentin.be@protonmail.com>
7
8//! Cache Level ID Register - EL1
9//!
10//! Identifies the type of cache, or caches, that are implemented at each level and can
11//! be managed using the architected cache maintenance instructions that operate by set/way,
12//! up to a maximum of seven levels. Also identifies the Level of Coherence (LoC) and Level
13//! of Unification (LoU) for the cache hierarchy.
14
15use tock_registers::{
16 interfaces::{Readable, Writeable},
17 register_bitfields,
18};
19
20register_bitfields! {u64,
21 pub CLIDR_EL1 [
22 /// **When FEAT_MTE2 is implemented:**
23 ///
24 /// Tag cache type 7. Indicates the type of cache that is implemented and can be
25 /// managed using the architected cache maintenance instructions that operate
26 /// by set/way at each level, from Level 1 up to a maximum of seven levels of
27 /// cache hierarchy.
28 ///
29 /// **Otherwise:**
30 ///
31 /// Reserved.
32 Ttype7 OFFSET(45) NUMBITS(2) [
33 /// No Tag Cache.
34 NoTag = 0b00,
35 /// Separate Allocation Tag Cache.
36 SeparateAllocationTag = 0b01,
37 /// Unified Allocation Tag and Data cache, Allocation Tags and Data in unified lines.
38 UnifiedAllocationTagDataCombined = 0b10,
39 /// Unified Allocation Tag and Data cache, Allocation Tags and Data in separate lines.
40 UnifiedAllocationTagDataSeparated = 0b11
41 ],
42
43 /// **When FEAT_MTE2 is implemented:**
44 ///
45 /// Tag cache type 6. Indicates the type of cache that is implemented and can be
46 /// managed using the architected cache maintenance instructions that operate
47 /// by set/way at each level, from Level 1 up to a maximum of seven levels of
48 /// cache hierarchy.
49 ///
50 /// **Otherwise:**
51 ///
52 /// Reserved.
53 Ttype6 OFFSET(43) NUMBITS(2) [
54 /// No Tag Cache.
55 NoTag = 0b00,
56 /// Separate Allocation Tag Cache.
57 SeparateAllocationTag = 0b01,
58 /// Unified Allocation Tag and Data cache, Allocation Tags and Data in unified lines.
59 UnifiedAllocationTagDataCombined = 0b10,
60 /// Unified Allocation Tag and Data cache, Allocation Tags and Data in separate lines.
61 UnifiedAllocationTagDataSeparated = 0b11
62 ],
63
64 /// **When FEAT_MTE2 is implemented:**
65 ///
66 /// Tag cache type 5. Indicates the type of cache that is implemented and can be
67 /// managed using the architected cache maintenance instructions that operate
68 /// by set/way at each level, from Level 1 up to a maximum of seven levels of
69 /// cache hierarchy.
70 ///
71 /// **Otherwise:**
72 ///
73 /// Reserved.
74 Ttype5 OFFSET(41) NUMBITS(2) [
75 /// No Tag Cache.
76 NoTag = 0b00,
77 /// Separate Allocation Tag Cache.
78 SeparateAllocationTag = 0b01,
79 /// Unified Allocation Tag and Data cache, Allocation Tags and Data in unified lines.
80 UnifiedAllocationTagDataCombined = 0b10,
81 /// Unified Allocation Tag and Data cache, Allocation Tags and Data in separate lines.
82 UnifiedAllocationTagDataSeparated = 0b11
83 ],
84
85 /// **When FEAT_MTE2 is implemented:**
86 ///
87 /// Tag cache type 4. Indicates the type of cache that is implemented and can be
88 /// managed using the architected cache maintenance instructions that operate
89 /// by set/way at each level, from Level 1 up to a maximum of seven levels of
90 /// cache hierarchy.
91 ///
92 /// **Otherwise:**
93 ///
94 /// Reserved.
95 Ttype4 OFFSET(39) NUMBITS(2) [
96 /// No Tag Cache.
97 NoTag = 0b00,
98 /// Separate Allocation Tag Cache.
99 SeparateAllocationTag = 0b01,
100 /// Unified Allocation Tag and Data cache, Allocation Tags and Data in unified lines.
101 UnifiedAllocationTagDataCombined = 0b10,
102 /// Unified Allocation Tag and Data cache, Allocation Tags and Data in separate lines.
103 UnifiedAllocationTagDataSeparated = 0b11
104 ],
105
106 /// **When FEAT_MTE2 is implemented:**
107 ///
108 /// Tag cache type 3. Indicates the type of cache that is implemented and can be
109 /// managed using the architected cache maintenance instructions that operate
110 /// by set/way at each level, from Level 1 up to a maximum of seven levels of
111 /// cache hierarchy.
112 ///
113 /// **Otherwise:**
114 ///
115 /// Reserved.
116 Ttype3 OFFSET(37) NUMBITS(2) [
117 /// No Tag Cache.
118 NoTag = 0b00,
119 /// Separate Allocation Tag Cache.
120 SeparateAllocationTag = 0b01,
121 /// Unified Allocation Tag and Data cache, Allocation Tags and Data in unified lines.
122 UnifiedAllocationTagDataCombined = 0b10,
123 /// Unified Allocation Tag and Data cache, Allocation Tags and Data in separate lines.
124 UnifiedAllocationTagDataSeparated = 0b11
125 ],
126
127 /// **When FEAT_MTE2 is implemented:**
128 ///
129 /// Tag cache type 2. Indicates the type of cache that is implemented and can be
130 /// managed using the architected cache maintenance instructions that operate
131 /// by set/way at each level, from Level 1 up to a maximum of seven levels of
132 /// cache hierarchy.
133 ///
134 /// **Otherwise:**
135 ///
136 /// Reserved.
137 Ttype2 OFFSET(35) NUMBITS(2) [
138 /// No Tag Cache.
139 NoTag = 0b00,
140 /// Separate Allocation Tag Cache.
141 SeparateAllocationTag = 0b01,
142 /// Unified Allocation Tag and Data cache, Allocation Tags and Data in unified lines.
143 UnifiedAllocationTagDataCombined = 0b10,
144 /// Unified Allocation Tag and Data cache, Allocation Tags and Data in separate lines.
145 UnifiedAllocationTagDataSeparated = 0b11
146 ],
147
148 /// **When FEAT_MTE2 is implemented:**
149 ///
150 /// Tag cache type 1. Indicates the type of cache that is implemented and can be
151 /// managed using the architected cache maintenance instructions that operate
152 /// by set/way at each level, from Level 1 up to a maximum of seven levels of
153 /// cache hierarchy.
154 ///
155 /// **Otherwise:**
156 ///
157 /// Reserved.
158 Ttype1 OFFSET(33) NUMBITS(2) [
159 /// No Tag Cache.
160 NoTag = 0b00,
161 /// Separate Allocation Tag Cache.
162 SeparateAllocationTag = 0b01,
163 /// Unified Allocation Tag and Data cache, Allocation Tags and Data in unified lines.
164 UnifiedAllocationTagDataCombined = 0b10,
165 /// Unified Allocation Tag and Data cache, Allocation Tags and Data in separate lines.
166 UnifiedAllocationTagDataSeparated = 0b11
167 ],
168
169 /// Inner cache boundary. This field indicates the boundary for caching
170 /// Inner Cacheable memory regions.
171 ICB OFFSET(30) NUMBITS(3) [
172 /// Not disclosed by this mechanism.
173 Undisclosed = 0b000,
174 /// L1 cache is the highest Inner Cacheable level.
175 HighestInnerCacheableL1 = 0b001,
176 /// L2 cache is the highest Inner Cacheable level.
177 HighestInnerCacheableL2 = 0b010,
178 /// L3 cache is the highest Inner Cacheable level.
179 HighestInnerCacheableL3 = 0b011,
180 /// L4 cache is the highest Inner Cacheable level.
181 HighestInnerCacheableL4 = 0b100,
182 /// L5 cache is the highest Inner Cacheable level.
183 HighestInnerCacheableL5 = 0b101,
184 /// L6 cache is the highest Inner Cacheable level.
185 HighestInnerCacheableL6 = 0b110,
186 /// L7 cache is the highest Inner Cacheable level.
187 HighestInnerCacheableL7 = 0b111
188 ],
189
190 /// Level of Unification Uniprocessor for the cache hierarchy.
191 ///
192 /// When FEAT_S2FWB is implemented, the architecture requires that this field
193 /// is zero so that no levels of data cache need to be cleaned in order to
194 /// manage coherency with instruction fetches.
195 LoUU OFFSET(27) NUMBITS(3) [],
196
197 /// Levels of Coherence for the cache hierarchy.
198 LoC OFFSET(24) NUMBITS(3) [],
199
200 /// Level of Unification Inner Shareable for the cache hierarchy.
201 ///
202 /// When FEAT_S2FWB is implemented, the architecture requires that this field
203 /// is zero so that no levels of data cache need to be cleaned in order to
204 /// manage coherency with instruction fetches.
205 LoUIS OFFSET(21) NUMBITS(3) [],
206
207 /// Cache Type field 7.
208 ///
209 /// Indicates the type of cache that is implemented and can be managed using
210 /// the architected cache maintenance instructions that operate by set/way at
211 /// each level, from Level 1 up to a maximum of seven levels of cache hierarchy.
212 ///
213 /// All values other than the defined ones are considered reserved.
214 ///
215 /// If software reads the Cache Type fields from [`CLIDR_EL1::Ctype1`] upwards,
216 /// once it has seen a value of `000`, no caches that can be managed using the
217 /// architected cache maintenance instructions that operate by set/way exist at
218 /// further-out levels of the hierarchy. So, for example, if Ctype3 is the first
219 /// Cache Type field with a value of `000`, the values of `Ctype4` to `Ctype7`
220 /// must be ignored.
221 Ctype7 OFFSET(18) NUMBITS(3) [
222 /// No cache.
223 NoCache = 0b000,
224 /// Instruction cache only.
225 InstructionCacheOnly = 0b001,
226 /// Data cache only.
227 DataCacheOnly = 0b010,
228 /// Separate instruction and data caches.
229 SeparateInstructionAndDataCaches = 0b011,
230 /// Unified cache.
231 UnifiedCache = 0b100
232 ],
233
234 /// Cache Type field 6.
235 ///
236 /// Indicates the type of cache that is implemented and can be managed using
237 /// the architected cache maintenance instructions that operate by set/way at
238 /// each level, from Level 1 up to a maximum of seven levels of cache hierarchy.
239 ///
240 /// All values other than the defined ones are considered reserved.
241 ///
242 /// If software reads the Cache Type fields from [`CLIDR_EL1::Ctype1`] upwards,
243 /// once it has seen a value of `000`, no caches that can be managed using the
244 /// architected cache maintenance instructions that operate by set/way exist at
245 /// further-out levels of the hierarchy. So, for example, if Ctype3 is the first
246 /// Cache Type field with a value of `000`, the values of `Ctype4` to `Ctype7`
247 /// must be ignored.
248 Ctype6 OFFSET(15) NUMBITS(3) [
249 /// No cache.
250 NoCache = 0b000,
251 /// Instruction cache only.
252 InstructionCacheOnly = 0b001,
253 /// Data cache only.
254 DataCacheOnly = 0b010,
255 /// Separate instruction and data caches.
256 SeparateInstructionAndDataCaches = 0b011,
257 /// Unified cache.
258 UnifiedCache = 0b100
259 ],
260
261 /// Cache Type field 5.
262 ///
263 /// Indicates the type of cache that is implemented and can be managed using
264 /// the architected cache maintenance instructions that operate by set/way at
265 /// each level, from Level 1 up to a maximum of seven levels of cache hierarchy.
266 ///
267 /// All values other than the defined ones are considered reserved.
268 ///
269 /// If software reads the Cache Type fields from [`CLIDR_EL1::Ctype1`] upwards,
270 /// once it has seen a value of `000`, no caches that can be managed using the
271 /// architected cache maintenance instructions that operate by set/way exist at
272 /// further-out levels of the hierarchy. So, for example, if Ctype3 is the first
273 /// Cache Type field with a value of `000`, the values of `Ctype4` to `Ctype7`
274 /// must be ignored.
275 Ctype5 OFFSET(12) NUMBITS(3) [
276 /// No cache.
277 NoCache = 0b000,
278 /// Instruction cache only.
279 InstructionCacheOnly = 0b001,
280 /// Data cache only.
281 DataCacheOnly = 0b010,
282 /// Separate instruction and data caches.
283 SeparateInstructionAndDataCaches = 0b011,
284 /// Unified cache.
285 UnifiedCache = 0b100
286 ],
287
288 /// Cache Type field 4.
289 ///
290 /// Indicates the type of cache that is implemented and can be managed using
291 /// the architected cache maintenance instructions that operate by set/way at
292 /// each level, from Level 1 up to a maximum of seven levels of cache hierarchy.
293 ///
294 /// All values other than the defined ones are considered reserved.
295 ///
296 /// If software reads the Cache Type fields from [`CLIDR_EL1::Ctype1`] upwards,
297 /// once it has seen a value of `000`, no caches that can be managed using the
298 /// architected cache maintenance instructions that operate by set/way exist at
299 /// further-out levels of the hierarchy. So, for example, if Ctype3 is the first
300 /// Cache Type field with a value of `000`, the values of `Ctype4` to `Ctype7`
301 /// must be ignored.
302 Ctype4 OFFSET(9) NUMBITS(3) [
303 /// No cache.
304 NoCache = 0b000,
305 /// Instruction cache only.
306 InstructionCacheOnly = 0b001,
307 /// Data cache only.
308 DataCacheOnly = 0b010,
309 /// Separate instruction and data caches.
310 SeparateInstructionAndDataCaches = 0b011,
311 /// Unified cache.
312 UnifiedCache = 0b100
313 ],
314
315 /// Cache Type field 3.
316 ///
317 /// Indicates the type of cache that is implemented and can be managed using
318 /// the architected cache maintenance instructions that operate by set/way at
319 /// each level, from Level 1 up to a maximum of seven levels of cache hierarchy.
320 ///
321 /// All values other than the defined ones are considered reserved.
322 ///
323 /// If software reads the Cache Type fields from [`CLIDR_EL1::Ctype1`] upwards,
324 /// once it has seen a value of `000`, no caches that can be managed using the
325 /// architected cache maintenance instructions that operate by set/way exist at
326 /// further-out levels of the hierarchy. So, for example, if Ctype3 is the first
327 /// Cache Type field with a value of `000`, the values of `Ctype4` to `Ctype7`
328 /// must be ignored.
329 Ctype3 OFFSET(6) NUMBITS(3) [
330 /// No cache.
331 NoCache = 0b000,
332 /// Instruction cache only.
333 InstructionCacheOnly = 0b001,
334 /// Data cache only.
335 DataCacheOnly = 0b010,
336 /// Separate instruction and data caches.
337 SeparateInstructionAndDataCaches = 0b011,
338 /// Unified cache.
339 UnifiedCache = 0b100
340 ],
341
342 /// Cache Type field 2.
343 ///
344 /// Indicates the type of cache that is implemented and can be managed using
345 /// the architected cache maintenance instructions that operate by set/way at
346 /// each level, from Level 1 up to a maximum of seven levels of cache hierarchy.
347 ///
348 /// All values other than the defined ones are considered reserved.
349 ///
350 /// If software reads the Cache Type fields from [`CLIDR_EL1::Ctype1`] upwards,
351 /// once it has seen a value of `000`, no caches that can be managed using the
352 /// architected cache maintenance instructions that operate by set/way exist at
353 /// further-out levels of the hierarchy. So, for example, if Ctype3 is the first
354 /// Cache Type field with a value of `000`, the values of `Ctype4` to `Ctype7`
355 /// must be ignored.
356 Ctype2 OFFSET(3) NUMBITS(3) [
357 /// No cache.
358 NoCache = 0b000,
359 /// Instruction cache only.
360 InstructionCacheOnly = 0b001,
361 /// Data cache only.
362 DataCacheOnly = 0b010,
363 /// Separate instruction and data caches.
364 SeparateInstructionAndDataCaches = 0b011,
365 /// Unified cache.
366 UnifiedCache = 0b100
367 ],
368
369 /// Cache Type field 1.
370 ///
371 /// Indicates the type of cache that is implemented and can be managed using
372 /// the architected cache maintenance instructions that operate by set/way at
373 /// each level, from Level 1 up to a maximum of seven levels of cache hierarchy.
374 ///
375 /// All values other than the defined ones are considered reserved.
376 ///
377 /// If software reads the Cache Type fields from [`CLIDR_EL1::Ctype1`] upwards,
378 /// once it has seen a value of `000`, no caches that can be managed using the
379 /// architected cache maintenance instructions that operate by set/way exist at
380 /// further-out levels of the hierarchy. So, for example, if Ctype3 is the first
381 /// Cache Type field with a value of `000`, the values of `Ctype4` to `Ctype7`
382 /// must be ignored.
383 Ctype1 OFFSET(0) NUMBITS(3) [
384 /// No cache.
385 NoCache = 0b000,
386 /// Instruction cache only.
387 InstructionCacheOnly = 0b001,
388 /// Data cache only.
389 DataCacheOnly = 0b010,
390 /// Separate instruction and data caches.
391 SeparateInstructionAndDataCaches = 0b011,
392 /// Unified cache.
393 UnifiedCache = 0b100
394 ]
395 ]
396}
397
398pub struct Reg;
399
400impl Readable for Reg {
401 type T = u64;
402 type R = CLIDR_EL1::Register;
403
404 sys_coproc_read_raw!(u64, "CLIDR_EL1", "x");
405}
406
407impl Writeable for Reg {
408 type T = u64;
409 type R = CLIDR_EL1::Register;
410
411 sys_coproc_write_raw!(u64, "CLIDR_EL1", "x");
412}
413
414pub const CLIDR_EL1: Reg = Reg;