aarch64_cpu/registers/sctlr_el3.rs
1// SPDX-License-Identifier: Apache-2.0 OR MIT
2//
3// Copyright (c) 2018-2023 by the author(s)
4//
5// Author(s):
6// - rmsyn <rmsynchls@gmail.com>
7
8//! System Control Register - EL3
9//!
10//! Provides top level control of the system, including its memory system, at EL3.
11
12use tock_registers::{
13 interfaces::{Readable, Writeable},
14 register_bitfields,
15};
16
17register_bitfields! {u64,
18 pub SCTLR_EL3 [
19
20 /// When FEAT_NMI is implemented:
21 ///
22 /// SP Interrupt Mask enable. When SCTLR_EL3.NMI is 1, controls whether PSTATE.SP acts as an
23 /// interrupt mask, and controls the value of PSTATE.ALLINT on taking an exception to EL3.
24 ///
25 /// 0b0 Does not cause PSTATE.SP to mask interrupts.
26 /// PSTATE.ALLINT is set to 1 on taking an exception to EL3
27 ///
28 /// 0b1 When PSTATE.SP is 1 and execution is at EL3, an IRQ or FIQ interrupt that is targeted
29 /// to EL3 is masked regardless of any denotion of Superpriority.
30 /// PSTATE.ALLINT is set to 0 on taking an exception to EL3.
31 ///
32 /// The reset behavior of this field is:
33 /// • On a Warm reset, in a system where the PE resets into EL3, this field resets to an
34 /// architecturally UNKNOWN value.
35 SPINTMASK OFFSET(62) NUMBITS(1) [
36 NoMask = 0,
37 Mask = 1
38 ],
39
40 /// When FEAT_NMI is implemented:
41 ///
42 /// Non-maskable Interrupt enable.
43 ///
44 /// 0b0 This control does not affect interrupt masking behavior.
45 ///
46 /// 0b1 This control enables all of the following:
47 /// • The use of the PSTATE.ALLINT interrupt mask.
48 /// • IRQ and FIQ interrupts to have Superpriority as an additional attribute.
49 /// • PSTATE.SP to be used as an interrupt mask.
50 ///
51 /// The reset behavior of this field is:
52 /// • On a Warm reset, in a system where the PE resets into EL3, this field resets to 0.
53 NMI OFFSET(61) NUMBITS(1) [
54 Disable = 0,
55 Enable = 1
56 ],
57
58 /// When FEAT_TME is implemented:
59 ///
60 /// Enables the Transactional Memory Extension at EL3.
61 ///
62 /// 0b0 Any attempt to execute a TSTART instruction at EL3 is trapped, unless HCR_EL2.TME
63 /// or SCR_EL3.TME causes TSTART instructions to be UNDEFINED at EL3.
64 ///
65 /// 0b1 This control does not cause any TSTART instruction to be trapped.
66 ///
67 /// The reset behavior of this field is:
68 /// • On a Warm reset, in a system where the PE resets into EL3, this field resets to an
69 /// architecturally UNKNOWN value.
70 TME OFFSET(53) NUMBITS(1) [
71 Trap = 0,
72 NoTrap = 1
73 ],
74
75 /// When FEAT_TME is implemented:
76 ///
77 /// Forces a trivial implementation of the Transactional Memory Extension at EL3.
78 ///
79 /// 0b0 This control does not cause any TSTART instruction to fail.
80 ///
81 /// 0b1 When the TSTART instruction is executed at EL3, the transaction fails with a TRIVIAL
82 /// failure cause.
83 ///
84 /// The reset behavior of this field is:
85 /// • On a Warm reset, in a system where the PE resets into EL3, this field resets to an
86 /// architecturally UNKNOWN value
87 TMT OFFSET(51) NUMBITS(1) [
88 NoFail = 0,
89 Fail = 1
90 ],
91
92 /// When FEAT_SSBS is implemented:
93 ///
94 /// Default PSTATE.SSBS value on Exception Entry.
95 ///
96 /// 0b0 PSTATE.SSBS is set to 0 on an exception to EL3.
97 ///
98 /// 0b1 PSTATE.SSBS is set to 1 on an exception to EL3.
99 ///
100 /// The reset behavior of this field is:
101 /// • On a Warm reset,this field resets to an IMPLEMENTATION DEFINED value.
102 DSSBS OFFSET(44) NUMBITS(1) [
103 SsbsUnset = 0,
104 SsbsSet = 1
105 ],
106
107 /// When FEAT_MTE2 is implemented:
108 ///
109 /// Allocation Tag Access in EL3.
110 ///
111 /// Controls access to Allocation Tags and Tag Check operations in EL3.
112 ///
113 /// 0b0 Access to Allocation Tags is prevented at EL3.
114 /// Memory accesses at EL3 are not subject to a Tag Check operation.
115 ///
116 /// 0b1 This control does not prevent access to Allocation Tags at EL3.
117 /// Tag Checked memory accesses at EL3 are subject to a Tag Check operation.
118 ///
119 /// The reset behavior of this field is:
120 /// • On a Warm reset, in a system where the PE resets into EL3, this field resets to an
121 /// architecturally UNKNOWN value.
122 ATA OFFSET(43) NUMBITS(1) [
123 Prevent = 0,
124 NoPrevent = 1
125 ],
126
127 /// When FEAT_MTE2 is implemented:
128 ///
129 /// Tag Check Fault in EL3. Controls the effect of Tag Check Faults due to Loads and Stores in EL3.
130 /// If FEAT_MTE3 is not implemented, the value 0b11 is reserved.
131 ///
132 /// 0b00 Tag Check Faults have no effect on the PE.
133 ///
134 /// 0b01 Tag Check Faults cause a synchronous exception.
135 ///
136 /// 0b10 Tag Check Faults are asynchronously accumulated.
137 ///
138 /// 0b11 When FEAT_MTE3 is implemented:
139 /// Tag Check Faults cause a synchronous exception on reads, and are asynchronously
140 /// accumulated on writes.
141 ///
142 /// The reset behavior of this field is:
143 /// • On a Warm reset, in a system where the PE resets into EL3, this field resets to an
144 /// architecturally UNKNOWN value.
145 TCF OFFSET(40) NUMBITS(2) [
146 NoEffect = 0,
147 SyncException = 1,
148 AsyncAccumulated = 2,
149 SyncReadAsyncWrite = 3
150 ],
151
152 /// When FEAT_MTE2 is implemented:
153 ///
154 /// When synchronous exceptions are not being generated by Tag Check Faults, this field controls
155 /// whether on exception entry into EL3, all Tag Check Faults due to instructions executed before
156 /// exception entry, that are reported asynchronously, are synchronized into TFSRE0_EL1 and
157 /// TFSR_ELx registers.
158 ///
159 /// 0b0 Tag Check Faults are not synchronized on entry to EL3.
160 ///
161 /// 0b1 Tag Check Faults are synchronized on entry to EL3.
162 ///
163 /// The reset behavior of this field is:
164 /// • On a Warm reset, in a system where the PE resets into EL3, this field resets to an
165 /// architecturally UNKNOWN value.
166 ITFSB OFFSET(37) NUMBITS(1) [
167 NoSyncEntry = 0,
168 SyncEntry = 1
169 ],
170
171 /// When FEAT_BTI is implemented:
172 ///
173 /// PAC Branch Type compatibility at EL3.
174 ///
175 /// 0b0 When the PE is executing at EL3, PACIASP and PACIBSP are compatible with
176 /// PSTATE.BTYPE == 0b11.
177 ///
178 /// 0b1 When the PE is executing at EL3, PACIASP and PACIBSP are not compatible with
179 /// PSTATE.BTYPE == 0b11.
180 ///
181 /// The reset behavior of this field is:
182 /// • On a Warm reset, in a system where the PE resets into EL3, this field resets to an
183 /// architecturally UNKNOWN value.
184 BT OFFSET(36) NUMBITS(1) [
185 Compat = 0,
186 NoCompat = 1
187 ],
188
189 /// When FEAT_PAuth is implemented:
190 ///
191 /// Controls enabling of pointer authentication (using the APIAKey_EL1 key) of instruction addresses
192 /// in the EL3 translation regime.
193 ///
194 /// Possible values of this bit are:
195 ///
196 /// 0b0 Pointer authentication (using the APIAKey_EL1 key) of instruction addresses is not
197 /// enabled.
198 ///
199 /// 0b1 Pointer authentication (using the APIAKey_EL1 key) of instruction addresses is
200 /// enabled.
201 ///
202 /// For more information, see Pointer authentication on page D5-4775.
203 ///
204 /// Note
205 ///
206 /// This field controls the behavior of the AddPACIA and AuthIA pseudocode functions. Specifically,
207 /// when the field is 1, AddPACIA returns a copy of a pointer to which a pointer authentication code
208 /// has been added, and AuthIA returns an authenticated copy of a pointer. When the field is 0, both of
209 /// these functions are NOP.
210 ///
211 /// The reset behavior of this field is:
212 /// • On a Warm reset, in a system where the PE resets into EL3, this field resets to an
213 /// architecturally UNKNOWN value.
214 EnIA OFFSET(31) NUMBITS(1) [
215 NotEnabled = 0,
216 Enabled = 1
217 ],
218
219 /// When FEAT_PAuth is implemented:
220 ///
221 /// Controls enabling of pointer authentication (using the APIBKey_EL1 key) of instruction addresses
222 /// in the EL3 translation regime.
223 ///
224 /// Possible values of this bit are:
225 ///
226 /// 0b0 Pointer authentication (using the APIBKey_EL1 key) of instruction addresses is not
227 /// enabled.
228 ///
229 /// 0b1 Pointer authentication (using the APIBKey_EL1 key) of instruction addresses is
230 /// enabled.
231 ///
232 /// For more information, see Pointer authentication on page D8-5164.
233 ///
234 /// Note
235 ///
236 /// This field controls the behavior of the AddPACIB and AuthIB pseudocode functions. Specifically,
237 /// when the field is 1, AddPACIB returns a copy of a pointer to which a pointer authentication code
238 /// has been added, and AuthIB returns an authenticated copy of a pointer. When the field is 0, both of
239 /// these functions are NOP.
240 ///
241 /// The reset behavior of this field is:
242 /// • On a Warm reset, in a system where the PE resets into EL3, this field resets to an
243 /// architecturally UNKNOWN value.
244 EnIB OFFSET(30) NUMBITS(1) [
245 NotEnabled = 0,
246 Enabled = 1
247 ],
248
249 /// When FEAT_PAuth is implemented:
250 ///
251 /// Controls enabling of pointer authentication (using the APDAKey_EL1 key) of instruction addresses
252 /// in the EL3 translation regime.
253 ///
254 /// 0b0 Pointer authentication (using the APDAKey_EL1 key) of data addresses is not enabled.
255 ///
256 /// 0b1 Pointer authentication (using the APDAKey_EL1 key) of data addresses is enabled.
257 ///
258 /// For more information, see Pointer authentication on page D8-5164.
259 ///
260 /// Note
261 ///
262 /// This field controls the behavior of the AddPACDA and AuthDA pseudocode functions. Specifically,
263 /// when the field is 1, AddPACDA returns a copy of a pointer to which a pointer authentication code
264 /// has been added, and AuthDA returns an authenticated copy of a pointer. When the field is 0, both
265 /// of these functions are NOP.
266 ///
267 /// The reset behavior of this field is:
268 /// • On a Warm reset, in a system where the PE resets into EL3, this field resets to an
269 /// architecturally UNKNOWN value.
270 EnDA OFFSET(27) NUMBITS(1) [
271 NotEnabled = 0,
272 Enabled = 1
273 ],
274
275 /// Endianness of data accesses at EL3, and stage 1 translation table walks in the EL3 translation
276 /// regime.
277 ///
278 /// 0b0 Explicit data accesses at EL3, and stage 1 translation table walks in the EL3 translation
279 /// regime are little-endian.
280 ///
281 /// 0b1 Explicit data accesses at EL3, and stage 1 translation table walks in the EL3 translation
282 /// regime are big-endian.
283 ///
284 /// If an implementation does not provide Big-endian support at Exception levels higher than EL0, this
285 /// bit is RES 0.
286 ///
287 /// If an implementation does not provide Little-endian support at Exception levels higher than EL0,
288 /// this bit is RES 1.
289 ///
290 /// The EE bit is permitted to be cached in a TLB.
291 ///
292 /// The reset behavior of this field is:
293 /// • On a Warm reset,this field resets to an IMPLEMENTATION DEFINED value.
294 EE OFFSET(25) NUMBITS(1) [
295 Little = 0,
296 Big = 1
297 ],
298
299 /// When FEAT_ExS is implemented:
300 ///
301 /// Exception Entry is Context Synchronizing.
302 ///
303 /// 0b0 The taking of an exception to EL3 is not a context synchronizing event.
304 ///
305 /// 0b1 The taking of an exception to EL3 is a context synchronizing event.
306 ///
307 /// If SCTLR_EL3.EIS is set to 0b0:
308 /// • Indirect writes to ESR_EL3, FAR_EL3, SPSR_EL3, ELR_EL3 are synchronized on
309 /// exception entry to EL3, so that a direct read of the register after exception entry sees the
310 /// indirectly written value caused by the exception entry.
311 ///
312 /// • Memory transactions, including instruction fetches, from an Exception level always use the
313 /// translation resources associated with that translation regime.
314 ///
315 /// • Exception Catch debug events are synchronous debug events.
316 ///
317 /// • DCPS* and DRPS instructions are context synchronization events.
318 /// The following are not affected by the value of SCTLR_EL3.EIS:
319 ///
320 /// • Changes to the PSTATE information on entry to EL3.
321 ///
322 /// • Behavior of accessing the banked copies of the stack pointer using the SP register name for
323 /// loads, stores and data processing instructions.
324 ///
325 /// • Debug state exit.
326 ///
327 /// The reset behavior of this field is:
328 /// • On a Warm reset, in a system where the PE resets into EL3, this field resets to an
329 /// architecturally UNKNOWN value.
330 EIS OFFSET(22) NUMBITS(1) [
331 NotContextSync = 0,
332 Context = 1
333 ],
334
335 /// When FEAT_IESB is implemented:
336 ///
337 /// Implicit Error Synchronization event enable.
338 ///
339 /// 0b0 Disabled.
340 ///
341 /// 0b1 An implicit error synchronization event is added:
342 ///
343 /// • At each exception taken to EL3.
344 ///
345 /// • Before the operational pseudocode of each ERET instruction executed at EL3.
346 ///
347 /// When the PE is in Debug state, the effect of this field is CONSTRAINED UNPREDICTABLE, and its
348 /// Effective value might be 0 or 1 regardless of the value of the field and, if implemented,
349 /// SCR_EL3.NMEA. If the Effective value of the field is 1, then an implicit error synchronization
350 /// event is added after each DCPSx instruction taken to EL3 and before each DRPS instruction executed
351 /// at EL3, in addition to the other cases where it is added.
352 ///
353 /// When FEAT_DoubleFault is implemented, the PE is in Non-debug state, and the Effective value of
354 /// SCR_EL3.NMEA is 1, this field is ignored and its Effective value is 1.
355 ///
356 /// The reset behavior of this field is:
357 /// • On a Warm reset, in a system where the PE resets into EL3, this field resets to an
358 /// architecturally UNKNOWN value.
359 IESB OFFSET(21) NUMBITS(1) [
360 Disabled = 0,
361 Enabled = 1
362 ],
363
364 /// Write permission implies XN (Execute-never). For the EL3 translation regime, this bit can force all
365 /// memory regions that are writable to be treated as XN.
366 ///
367 /// 0b0 This control has no effect on memory access permissions.
368 ///
369 /// 0b1 Any region that is writable in the EL3 translation regime is forced to XN for accesses
370 /// from software executing at EL3.
371 ///
372 /// This bit applies only when SCTLR_EL3.M bit is set.
373 ///
374 /// The WXN bit is permitted to be cached in a TLB.
375 ///
376 /// The reset behavior of this field is:
377 /// • On a Warm reset, in a system where the PE resets into EL3, this field resets to an
378 /// architecturally UNKNOWN value.
379 WXN OFFSET(19) NUMBITS(1) [
380 Disabled = 0,
381 Enabled = 1
382 ],
383
384 /// When FEAT_PAuth is implemented:
385 ///
386 /// Controls enabling of pointer authentication (using the APDBKey_EL1 key) of instruction addresses
387 /// in the EL3 translation regime.
388 ///
389 /// 0b0 Pointer authentication (using the APDBKey_EL1 key) of data addresses is not enabled.
390 ///
391 /// 0b1 Pointer authentication (using the APDBKey_EL1 key) of data addresses is enabled.
392 ///
393 /// For more information, see Pointer authentication on page D8-5164.
394 ///
395 /// Note
396 ///
397 /// This field controls the behavior of the AddPACDB and AuthDB pseudocode functions. Specifically,
398 /// when the field is 1, AddPACDB returns a copy of a pointer to which a pointer authentication code
399 /// has been added, and AuthDB returns an authenticated copy of a pointer. When the field is 0, both of
400 /// these functions are NOP.
401 ///
402 /// The reset behavior of this field is:
403 /// • On a Warm reset, in a system where the PE resets into EL3, this field resets to an
404 /// architecturally UNKNOWN value.
405 EnDB OFFSET(13) NUMBITS(1) [
406 Disabled = 0,
407 Enabled = 1
408 ],
409
410 /// Instruction access Cacheability control, for accesses at EL3:
411 ///
412 /// 0b0 All instruction access to Normal memory from EL3 are Non-cacheable for all levels of
413 /// instruction and unified cache.
414 ///
415 /// If the value of SCTLR_EL3.M is 0, instruction accesses from stage 1 of the EL3
416 /// translation regime are to Normal, Outer Shareable, Inner Non-cacheable, Outer
417 /// Non-cacheable memory.
418 ///
419 /// 0b1 This control has no effect on the Cacheability of instruction access to Normal memory
420 /// from EL3.
421 ///
422 /// If the value of SCTLR_EL3.M is 0, instruction accesses from stage 1 of the EL3
423 /// translation regime are to Normal, Outer Shareable, Inner Write-Through, Outer
424 /// Write-Through memory.
425 ///
426 /// This bit has no effect on the EL1&0, EL2, or EL2&0 translation regimes.
427 ///
428 /// The reset behavior of this field is:
429 /// • On a Warm reset, in a system where the PE resets into EL3, this field resets to 0.
430 I OFFSET(12) NUMBITS(1) [
431 Enabled = 0,
432 Disabled = 1
433 ],
434
435 /// When FEAT_ExS is implemented:
436 ///
437 /// Exception Exit is Context Synchronizing.
438 ///
439 /// 0b0 An exception return from EL3 is not a context synchronizing event
440 ///
441 /// 0b1 An exception return from EL3 is a context synchronizing event
442 ///
443 /// If SCTLR_EL3.EOS is set to 0b0:
444 /// • Memory transactions, including instruction fetches, from an Exception level always use the
445 /// translation resources associated with that translation regime.
446 ///
447 /// • Exception Catch debug events are synchronous debug events.
448 ///
449 /// • DCPS* and DRPS instructions are context synchronization events.
450 /// The following are not affected by the value of SCTLR_EL3.EOS:
451 ///
452 /// • The indirect write of the PSTATE and PC values from SPSR_EL3 and ELR_EL3 on
453 /// exception return is synchronized.
454 ///
455 /// • If the PE enters Debug state before the first instruction after an Exception return from EL3
456 /// to Non-secure state, any pending Halting debug event completes execution.
457 ///
458 /// • The GIC behavior that allocates interrupts to FIQ or IRQ changes simultaneously with
459 /// leaving the EL3 Exception level.
460 ///
461 /// • Behavior of accessing the banked copies of the stack pointer using the SP register name for
462 /// loads, stores and data processing instructions.
463 ///
464 /// • Exit from Debug state.
465 ///
466 /// The reset behavior of this field is:
467 /// • On a Warm reset, in a system where the PE resets into EL3, this field resets to an
468 /// architecturally UNKNOWN value.
469 EOS OFFSET(11) NUMBITS(1) [
470 NotContextSync = 0,
471 ContextSync = 1
472 ],
473
474 /// When FEAT_LSE2 is implemented:
475 ///
476 /// Non-aligned access. This bit controls generation of Alignment faults at EL3 under certain
477 /// conditions. The following instructions generate an Alignment fault if all bytes being accessed are
478 /// not within a single 16-byte quantity, aligned to 16 bytes for access:
479 ///
480 /// • LDAPR, LDAPRH, LDAPUR, LDAPURH, LDAPURSH, LDAPURSW, LDAR, LDARH,
481 /// LDLAR, LDLARH.
482 ///
483 /// • STLLR, STLLRH, STLR, STLRH, STLUR, and STLURH
484 ///
485 /// 0b0 Unaligned accesses by the specified instructions generate an Alignment fault.
486 ///
487 /// 0b1 Unaligned accesses by the specified instructions do not generate an Alignment fault.
488 ///
489 /// The reset behavior of this field is:
490 /// • On a Warm reset, in a system where the PE resets into EL3, this field resets to an
491 /// architecturally UNKNOWN value.
492 nAA OFFSET(6) NUMBITS(1) [
493 Fault = 0,
494 NoFault = 1
495 ],
496
497 /// SP Alignment check enable. When set to 1, if a load or store instruction executed at EL3 uses the
498 /// SP as the base address and the SP is not aligned to a 16-byte boundary, then a SP alignment fault
499 /// exception is generated. For more information, see SP alignment checking on page D1-4668.
500 ///
501 /// The reset behavior of this field is:
502 /// • On a Warm reset, in a system where the PE resets into EL3, this field resets to an
503 /// architecturally UNKNOWN value.
504 SA OFFSET(3) NUMBITS(1) [
505 NoFault = 0,
506 Fault = 1
507 ],
508
509 /// Cacheability control, for data accesses.
510 ///
511 /// 0b0 All data access to Normal memory from EL3, and all Normal memory accesses to the
512 /// EL3 translation tables, are Non-cacheable for all levels of data and unified cache.
513 ///
514 /// 0b1 This control has no effect on the Cacheability of:
515 /// • Data access to Normal memory from EL3.
516 /// • Normal memory accesses to the EL3 translation tables.
517 ///
518 /// This bit has no effect on the EL1&0, EL2, or EL2&0 translation regimes.
519 ///
520 /// The reset behavior of this field is:
521 /// • On a Warm reset, in a system where the PE resets into EL3, this field resets to 0.
522 C OFFSET(2) NUMBITS(1) [
523 Enabled = 0,
524 Disabled = 1
525 ],
526
527 /// Alignment check enable. This is the enable bit for Alignment fault checking at EL3.
528 ///
529 /// 0b0 Alignment fault checking disabled when executing at EL3.
530 /// Instructions that load or store one or more registers, other than load/store exclusive and
531 /// load-acquire/store-release, do not check that the address being accessed is aligned to the
532 /// size of the data element(s) being accessed.
533 ///
534 /// 0b1 Alignment fault checking enabled when executing at EL3.
535 /// All instructions that load or store one or more registers have an alignment check that the
536 /// address being accessed is aligned to the size of the data element(s) being accessed. If
537 /// this check fails it causes an Alignment fault, which is taken as a Data Abort exception.
538 ///
539 /// Load/store exclusive and load-acquire/store-release instructions have an alignment check regardless
540 /// of the value of the A bit.
541 ///
542 /// If FEAT_MOPS is implemented,SETG* instructions have an alignment check regardless of the
543 /// value of the A bit.
544 ///
545 /// The reset behavior of this field is:
546 /// • On a Warm reset, in a system where the PE resets into EL3, this field resets to an
547 /// architecturally UNKNOWN value.
548 A OFFSET(1) NUMBITS(1) [
549 Disabled = 0,
550 Enabled = 1
551 ],
552
553 /// MMU enable for EL3 stage 1 address translation. Possible values of this bit are:
554 ///
555 /// 0b0 EL3 stage 1 address translation disabled.
556 /// See the SCTLR_EL3.I field for the behavior of instruction accesses to Normal memory.
557 ///
558 /// 0b1 EL3 stage 1 address translation enabled.
559 ///
560 /// The reset behavior of this field is:
561 /// • On a Warm reset, in a system where the PE resets into EL3, this field resets to 0.
562 M OFFSET(0) NUMBITS(1) [
563 Disabled = 0,
564 Enabled = 1
565 ]
566 ]
567}
568
569pub struct Reg;
570
571impl Readable for Reg {
572 type T = u64;
573 type R = SCTLR_EL3::Register;
574
575 sys_coproc_read_raw!(u64, "SCTLR_EL3", "x");
576}
577
578impl Writeable for Reg {
579 type T = u64;
580 type R = SCTLR_EL3::Register;
581
582 sys_coproc_write_raw!(u64, "SCTLR_EL3", "x");
583}
584
585pub const SCTLR_EL3: Reg = Reg {};