aarch32_cpu/register/
dfsr.rs

1//! Code for managing DFSR (*Data Fault Status Register*)
2
3#[cfg(arm_architecture = "v6")]
4use arbitrary_int::u4;
5
6use crate::register::{SysReg, SysRegRead, SysRegWrite};
7
8/// DFSR (*Data Fault Status Register*)
9#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
10#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
11#[cfg(arm_architecture = "v5te")]
12pub struct Dfsr {
13    /// Status
14    #[bits([0..=3], rw)]
15    status: Option<DfsrStatus>,
16}
17
18/// DFSR (*Data Fault Status Register*)
19#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
20#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
21#[cfg(arm_architecture = "v6")]
22pub struct Dfsr {
23    /// Write not Read
24    #[bit(11, rw)]
25    wnr: bool,
26    /// Domain
27    #[bits(4..=7, rw)]
28    domain: u4,
29    /// Status bitfield.
30    #[bits([0..=3, 10], rw)]
31    status: Option<DfsrStatus>,
32}
33
34/// DFSR (*Data Fault Status Register*)
35#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
36#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
37#[cfg(arm_architecture = "v7-r")]
38pub struct Dfsr {
39    /// Status bitfield.
40    #[bits([0..=3, 10], rw)]
41    status: Option<DfsrStatus>,
42}
43
44/// DFSR (*Instruction Fault Status Register*)
45#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
46#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
47#[cfg(arm_architecture = "v7-a")]
48pub struct Dfsr {
49    /// FAR not Valid
50    #[bit(16, rw)]
51    fnv: bool,
52    /// Cache manintenance fault
53    #[bit(13, rw)]
54    cm: bool,
55    /// External Abort type
56    #[bit(12, rw)]
57    ext: bool,
58    /// Write not Read
59    #[bit(11, rw)]
60    wnr: bool,
61    /// Status bitfield.
62    #[bits([0..=5], rw)]
63    status: Option<DfsrStatus>,
64}
65
66/// DFSR (*Data Fault Status Register*)
67#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
68#[cfg(arm_architecture = "v8-r")]
69pub struct Dfsr {
70    /// FAR not Valid
71    #[bit(16, rw)]
72    fnv: bool,
73    /// Cache manintenance fault
74    #[bit(13, rw)]
75    cm: bool,
76    /// External Abort type
77    #[bit(12, rw)]
78    ext: bool,
79    /// Write not Read
80    #[bit(11, rw)]
81    wnr: bool,
82    /// Status bitfield.
83    #[bits([0..=5], rw)]
84    status: Option<DfsrStatus>,
85}
86
87/// Fault status register enumeration for DFSR
88#[bitbybit::bitenum(u4, exhaustive = false)]
89#[cfg_attr(feature = "defmt", derive(defmt::Format))]
90#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
91#[cfg(arm_architecture = "v5te")]
92#[derive(Debug, PartialEq, Eq)]
93#[repr(u8)]
94pub enum DfsrStatus {
95    /// Alignment fault
96    AlignmentFault = 1,
97    /// Debug Exception
98    Debug = 2,
99    /// Alternate value for Alignment fault
100    AlignmentAlt = 3,
101    /// Translation fault, level 1
102    TranslationFaultFirstLevel = 5,
103    /// Translation fault, level 2
104    TranslationFaultSecondLevel = 7,
105    /// Synchronous External Abort
106    SyncExtAbort = 8,
107    /// Domain fault, level 1
108    DomainFaultFirstLevel = 9,
109    /// Alternate value for Synchronous External Abort
110    SyncExtAbortAlt = 10,
111    /// Domain fault, level 2
112    DomainFaultSecondLevel = 11,
113    /// Synchronous External abort, on translation table walk, level 1
114    SyncExtAbortOnTranslationTableWalkFirstLevel = 12,
115    /// Permission fault, level 1
116    PermissionFaultFirstLevel = 13,
117    /// Synchronous External abort, on translation table walk, level 2
118    SyncExtAbortOnTranslationTableWalkSecondLevel = 14,
119    /// Permission fault, level 2
120    PermissionFaultSecondLevel = 15,
121}
122
123/// Fault status register enumeration for DFSR
124#[bitbybit::bitenum(u5, exhaustive = false)]
125#[cfg_attr(feature = "defmt", derive(defmt::Format))]
126#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
127#[cfg(arm_architecture = "v6")]
128#[derive(Debug, PartialEq, Eq)]
129#[repr(u8)]
130pub enum DfsrStatus {
131    /// Alignment fault
132    AlignmentFault = 0b00001,
133    /// Debug event fault
134    Debug = 0b00010,
135    /// Access Flag fault on Section
136    AccessFlagFaultFirstLevel = 0b00011,
137    /// Cache maintenance operation fault
138    CacheMaintenance = 0b00100,
139    /// Translation fault on Section
140    TranslationFaultFirstLevel = 0b00101,
141    /// Access Flag fault on Page
142    AccessFlagFaultSecondLevel = 0b00110,
143    /// Translation fault on Page
144    TranslationFaultSecondLevel = 0b00111,
145    /// Precise External Abort
146    PreciseExternalAbort = 0b01000,
147    /// Domain fault on Section
148    DomainFaultFirstLevel = 0b01001,
149    /// Domain fault on Page
150    DomainFaultSecondLevel = 0b01011,
151    /// External abort on translation, first level
152    SyncExtAbortOnTranslationTableWalkFirstLevel = 0b01100,
153    /// Permission fault on Section
154    PermissionFaultFirstLevel = 0b01101,
155    /// External abort on translation, second level
156    SyncExtAbortOnTranslationTableWalkSecondLevel = 0b01110,
157    /// Permission fault on Page
158    PermissionFaultSecondLevel = 0b01111,
159    /// Imprecise External Abort
160    ImpreciseExtAbort = 0b10110,
161}
162
163/// Fault status register enumeration for DFSR
164#[bitbybit::bitenum(u5, exhaustive = false)]
165#[cfg_attr(feature = "defmt", derive(defmt::Format))]
166#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
167#[cfg(arm_architecture = "v7-r")]
168#[derive(Debug, PartialEq, Eq)]
169#[repr(u8)]
170pub enum DfsrStatus {
171    /// Alignment fault
172    AlignmentFault = 1,
173    /// Debug exception
174    Debug = 2,
175    /// Translation fault
176    Translation = 4,
177    /// Permission fault
178    Permission = 12,
179    /// Synchronous external abort, other than synchronous parity or ECC error
180    SError = 16,
181    /// SError interrupt
182    SErrorInterrupt = 17,
183    /// Synchronous parity or ECC error on memory access
184    SyncParErrorOnMemAccess = 24,
185    /// SError parity or ECC error on memory access
186    SErrorParityEccError = 25,
187}
188
189/// Fault status register enumeration for DFSR
190#[bitbybit::bitenum(u6, exhaustive = false)]
191#[cfg_attr(feature = "defmt", derive(defmt::Format))]
192#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
193#[cfg(arm_architecture = "v7-a")]
194#[derive(Debug, PartialEq, Eq)]
195#[repr(u8)]
196pub enum DfsrStatus {
197    /// Alignment fault.
198    AlignmentFault = 0b00001,
199    /// Debug exception.
200    Debug = 0b00010,
201    /// Access flag fault, level 1
202    AccessFlagFaultFirstLevel = 0b00011,
203    /// Fault on instruction cache maintenance.
204    CacheMaintenance = 0b00100,
205    /// Translation fault, level 1
206    TranslationFaultFirstLevel = 0b00101,
207    /// Access flag fault, level 2.
208    AccessFlagFaultSecondLevel = 0b00110,
209    /// Translation fault, level 2.
210    TranslationFaultSecondLevel = 0b00111,
211    /// Synchronous External abort, not on translation table walk.
212    SyncExtAbort = 0b01000,
213    /// Domain fault, level 1
214    DomainFaultFirstLevel = 0b01001,
215    /// Domain fault, level 2.
216    DomainFaultSecondLevel = 0b01011,
217    /// Synchronous External abort, on translation table walk, level 1
218    SyncExtAbortOnTranslationTableWalkFirstLevel = 0b01100,
219    /// Permission fault, level 1
220    PermissionFaultFirstLevel = 0b01101,
221    /// Synchronous External abort, on translation table walk, level 2.
222    SyncExtAbortOnTranslationTableWalkSecondLevel = 0b01110,
223    /// Permission fault, level 2.
224    PermissionFaultSecondLevel = 0b01111,
225    /// TLB conflict abort.
226    TldConflictAbort = 0b10000,
227    /// SError exception.
228    SError = 0b10110,
229    /// SError exception, from a parity or ECC error on memory access.
230    SErrorParityEccError = 0b11000,
231    /// Synchronous parity or ECC error on memory access, not on translation table walk.
232    SyncParErrorOnMemAccess = 0b11001,
233    /// Synchronous parity or ECC error on translation table walk, level 1
234    SyncParErrorOnTranslationTableWalkFirstLevel = 0b11100,
235    /// Synchronous parity or ECC error on translation table walk, level 2.
236    SyncParErrorOnTranslationTableWalkSecondLevel = 0b11110,
237}
238
239/// Fault status register enumeration for DFSR
240#[bitbybit::bitenum(u6, exhaustive = false)]
241#[cfg_attr(feature = "defmt", derive(defmt::Format))]
242#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
243#[cfg(arm_architecture = "v8-r")]
244#[derive(Debug, PartialEq, Eq)]
245#[repr(u8)]
246pub enum DfsrStatus {
247    /// Translation fault
248    Translation = 4,
249    /// Permission fault
250    Permission = 12,
251    /// Synchronous external abort, other than synchronous parity or ECC error
252    SyncExtAbort = 16,
253    /// SError interrupt
254    SErrorInterrupt = 17,
255    /// Synchronous parity or ECC error on memory access
256    SyncParityEccError = 24,
257    /// SError parity or ECC error on memory access
258    SErrorParityEccError = 25,
259    /// Alignment fault
260    AlignmentFault = 33,
261    /// Debug exception
262    Debug = 34,
263}
264
265impl SysReg for Dfsr {
266    const CP: u32 = 15;
267    const CRN: u32 = 5;
268    const OP1: u32 = 0;
269    const CRM: u32 = 0;
270    const OP2: u32 = 0;
271}
272
273impl crate::register::SysRegRead for Dfsr {}
274
275impl Dfsr {
276    #[inline]
277    /// Reads DFSR (*Data Fault Status Register*)
278    pub fn read() -> Dfsr {
279        Self::new_with_raw_value(<Self as SysRegRead>::read_raw())
280    }
281}
282
283impl crate::register::SysRegWrite for Dfsr {}
284
285impl Dfsr {
286    #[inline]
287    /// Writes DFSR (*Data Fault Status Register*)
288    ///
289    /// # Safety
290    ///
291    /// Ensure that this value is appropriate for this register
292    pub unsafe fn write(value: Self) {
293        unsafe {
294            <Self as SysRegWrite>::write_raw(value.raw_value());
295        }
296    }
297}
aarch32_cpu/register/dfsr.rs

aarch32_cpu/register/
dfsr.rs
