aarch32_cpu/register/
vbar.rs

1//! Code for managing VBAR (*Vector Base Address Register*)
2
3use crate::register::{SysReg, SysRegRead, SysRegWrite};
4
5/// VBAR (*Vector Base Address Register*)
6///
7/// There is no `modify` method because this register holds a single 32-bit address.
8#[derive(Debug, Clone, Copy, PartialEq, Eq)]
9#[repr(transparent)]
10#[cfg_attr(feature = "defmt", derive(defmt::Format))]
11#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
12pub struct Vbar(pub u32);
13
14impl SysReg for Vbar {
15    const CP: u32 = 15;
16    const CRN: u32 = 12;
17    const OP1: u32 = 0;
18    const CRM: u32 = 0;
19    const OP2: u32 = 0;
20}
21
22impl SysRegRead for Vbar {}
23
24impl SysRegWrite for Vbar {}
25
26impl Vbar {
27    /// Read VBAR (*Vector Base Address Register*)
28    #[inline]
29    pub fn read() -> Vbar {
30        Self(<Self as SysRegRead>::read_raw())
31    }
32
33    /// Write VBAR (*Vector Base Address Register*)
34    ///
35    /// # Safety
36    ///
37    /// You must supply a correctly-aligned address of a valid Arm AArch32
38    /// Vector Table.
39    #[inline]
40    pub unsafe fn write(value: Self) {
41        // Safety: Writing this register is atomic
42        unsafe {
43            <Self as SysRegWrite>::write_raw(value.0);
44        }
45    }
46}
aarch32_cpu/register/vbar.rs

aarch32_cpu/register/
vbar.rs
