aarch32_cpu/register/
ttbr0.rs

1//! Code for managing TTBR0 (*Translation Table Base Register 0*)
2
3use arbitrary_int::u25;
4
5use crate::register::{SysReg, SysRegRead, SysRegWrite};
6
7/// TTBR0 (*Translation Table Base Register 0*)
8#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
9#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
10pub struct Ttbr0 {
11    /// Translation table base 0 address
12    ///
13    /// The actual width can vary from 7..=31 to 14..=31, depending on the value
14    /// of TTBCR.N.
15    #[bits(7..=31, rw)]
16    addr: u25,
17
18    /// Inner Region
19    ///
20    /// See docs for the [`Ttbr0::c`] bit.
21    #[bit(6, rw)]
22    irgn: bool,
23
24    /// Not Outer Shareable
25    ///
26    /// Ignored when [`Ttbr0::s`] is `false`.
27    #[bit(5, rw)]
28    nos: bool,
29
30    /// Region bits
31    ///
32    /// Indicates the Outer cacheability attributes for the memory associated
33    /// with the translation table walks.
34    #[bits(3..=4, rw)]
35    rgn: Region,
36
37    /// Shareable
38    #[bit(1, rw)]
39    s: bool,
40
41    /// Cacheable
42    ///
43    /// * c = false => Inner Non-cacheable
44    /// * c = true => Inner Cacheable
45    ///
46    /// On a multi-processor system, set this in conjunction with `irgn` as follows:
47    ///
48    /// * c = false, irgn = false => Normal memory, Inner Non-cacheable
49    /// * c = true, irgn = false => Normal memory, Inner Write-Through Cacheable
50    /// * c = false, irgn = true => Normal memory, Inner Write-Back Write-Allocate Cacheable
51    /// * c = true, irgn = true => Normal memory, Inner Write-Back no Write-Allocate Cacheable
52    #[bit(0, rw)]
53    c: bool,
54}
55
56impl Ttbr0 {
57    /// Get the address
58    ///
59    /// Returns a full 32-bit memory address.
60    pub fn get_address(&self) -> usize {
61        (self.raw_value() & 0xFFFF_FF80) as usize
62    }
63
64    /// Set the address
65    ///
66    /// Pass a full 32-bit memory address. It will be shifted before being stored in this value.
67    pub fn set_address(&mut self, address: usize) {
68        let addr = u25::from_u32((address >> 7) as u32);
69        self.set_addr(addr);
70    }
71
72    /// Change the address
73    ///
74    /// Pass a full 32-bit memory address. It will be shifted before being stored in the returned value.
75    pub fn with_address(self, address: usize) -> Self {
76        let addr = u25::from_u32((address >> 7) as u32);
77        self.with_addr(addr)
78    }
79}
80
81/// Outer cacheability attributes
82#[derive(Debug)]
83#[bitbybit::bitenum(u2, exhaustive = true)]
84#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
85#[cfg_attr(feature = "defmt", derive(defmt::Format))]
86pub enum Region {
87    /// Normal memory, Outer Non-cacheable
88    NonCacheable = 0b00,
89    /// Normal memory, Outer Write-Back Write-Allocate Cacheable
90    WriteBackWriteAllocCacheable = 0b01,
91    /// Normal memory, Outer Write-Through Cacheable
92    WriteThroughCacheable = 0b10,
93    /// Normal memory, Outer Write-Back no Write-Allocate Cacheable
94    WriteBackNoWriteAllocCacheable = 0b11,
95}
96
97impl SysReg for Ttbr0 {
98    const CP: u32 = 15;
99    const CRN: u32 = 2;
100    const OP1: u32 = 0;
101    const CRM: u32 = 0;
102    const OP2: u32 = 0;
103}
104
105impl crate::register::SysRegRead for Ttbr0 {}
106
107impl crate::register::SysRegWrite for Ttbr0 {}
108
109impl Ttbr0 {
110    #[inline]
111    /// Reads TTBR0 (*Translation Table Base Register 0*)
112    pub fn read() -> Ttbr0 {
113        Self::new_with_raw_value(<Self as SysRegRead>::read_raw())
114    }
115
116    #[inline]
117    /// Writes TTBR0 (*Translation Table Base Register 0*)
118    ///
119    /// # Safety
120    ///
121    /// Ensure that this value is appropriate for this register
122    pub unsafe fn write(value: Self) {
123        unsafe {
124            <Self as SysRegWrite>::write_raw(value.raw_value());
125        }
126    }
127}
aarch32_cpu/register/ttbr0.rs

aarch32_cpu/register/
ttbr0.rs
