aarch32_cpu/register/
sctlr.rs

1//! Code for managing SCTLR (*System Control Register*)
2
3use super::{SysReg, SysRegRead, SysRegWrite};
4
5/// SCTLR (*System Control Register*)
6#[bitbybit::bitfield(u32)]
7#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
8pub struct Sctlr {
9    /// The bitmask for the Instruction Endianness bit
10    #[bits(31..=31, rw)]
11    ie: bool,
12    /// The bitmask for the Thumb Exception Enable bit
13    #[bits(30..=30, rw)]
14    te: bool,
15    /// The bitmask for the Non-Maskable FIQ bit
16    #[bits(27..=27, rw)]
17    nmfi: bool,
18    /// The bitmask for the Exception Endianness bit
19    #[bits(25..=25, rw)]
20    ee: bool,
21    /// The bitmask for the U bit
22    #[bits(22..=22, rw)]
23    u: bool,
24    /// The bitmask for the Fast Interrupt bit
25    #[bits(21..=21, rw)]
26    fi: bool,
27    /// The bitmask for the Divide by Zero Fault bit
28    #[bits(18..=18, rw)]
29    dz: bool,
30    /// The bitmask for the Background Region bit
31    #[bits(17..=17, rw)]
32    br: bool,
33    /// The bitmask for the Round Robin bit
34    #[bits(14..=14, rw)]
35    rr: bool,
36    /// The bitmask for the Exception Vector Table bit
37    #[bits(13..=13, rw)]
38    v: bool,
39    /// The bitmask for the Instruction Cache enable bit
40    #[bits(12..=12, rw)]
41    i: bool,
42    /// The bitmask for the Branch Prediction enable bit
43    #[bits(11..=11, rw)]
44    z: bool,
45    /// The bitmask for the SWP bit
46    #[bits(10..=10, rw)]
47    sw: bool,
48    /// The bitmask for the Cache enable bit
49    #[bits(2..=2, rw)]
50    c: bool,
51    /// The bitmask for the Alignment check bit
52    #[bits(1..=1, rw)]
53    a: bool,
54    /// The bitmask for the MPU bit
55    #[bits(0..=0, rw)]
56    m: bool,
57}
58
59impl SysReg for Sctlr {
60    const CP: u32 = 15;
61    const CRN: u32 = 1;
62    const OP1: u32 = 0;
63    const CRM: u32 = 0;
64    const OP2: u32 = 0;
65}
66
67impl SysRegRead for Sctlr {}
68
69impl SysRegWrite for Sctlr {}
70
71impl Sctlr {
72    /// Read SCTLR (*System Control Register*)
73    #[inline]
74    pub fn read() -> Self {
75        Self::new_with_raw_value(<Self as SysRegRead>::read_raw())
76    }
77
78    /// Write SCTLR (*System Control Register*)
79    #[inline]
80    pub fn write(_value: Self) {
81        // Safety: Writing this register is atomic
82        unsafe {
83            <Self as SysRegWrite>::write_raw(_value.raw_value());
84        }
85    }
86
87    /// Modify SCTLR (*System Control Register*)
88    #[inline]
89    pub fn modify<F>(f: F)
90    where
91        F: FnOnce(&mut Self),
92    {
93        let mut value = Self::read();
94        f(&mut value);
95        Self::write(value);
96        // flush the pipeline on Armv7-A, in case they changed the MMU bit
97        #[cfg(arm_architecture = "v7-a")]
98        unsafe {
99            core::arch::asm!("dsb");
100            core::arch::asm!("isb");
101        }
102    }
103}
104
105impl core::fmt::Debug for Sctlr {
106    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
107        write!(
108            f,
109            "SCTLR {{ IE={} TE={} NMFI={} EE={} U={} FI={} DZ={} BR={} RR={} V={} I={} Z={} SW={} C={} A={} M={} }}",
110            self.ie() as u8,
111            self.te() as u8,
112            self.nmfi() as u8,
113            self.ee() as u8,
114            self.u() as u8,
115            self.fi() as u8,
116            self.dz() as u8,
117            self.br() as u8,
118            self.rr() as u8,
119            self.v() as u8,
120            self.i() as u8,
121            self.z() as u8,
122            self.sw() as u8,
123            self.c() as u8,
124            self.a() as u8,
125            self.m() as u8,
126        )
127    }
128}
129
130#[cfg(feature = "defmt")]
131impl defmt::Format for Sctlr {
132    fn format(&self, f: defmt::Formatter) {
133        defmt::write!(f, "SCTLR {{ IE={0=31..32} TE={0=30..31} NMFI={0=27..28} EE={0=25..26} U={0=22..23} FI={0=21..22} DZ={0=18..19} BR={0=17..18} RR={0=14..15} V={0=13..14} I={0=12..13} Z={0=11..12} SW={0=10..11} C={0=2..3} A={0=1..2} M={0=0..1} }}", self.raw_value())
134    }
135}
aarch32_cpu/register/sctlr.rs

aarch32_cpu/register/
sctlr.rs
