aarch32_cpu/register/
mair0.rs

1//! Code for managing MAIR0 (*Memory Attribute Indirection Register 0*)
2
3use crate::register::{SysReg, SysRegRead, SysRegWrite};
4
5/// MAIR (*Memory Attribute Indirection Register*) value for MAIR0 or MAIR1
6#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
7#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
8pub struct Mair {
9    /// The four MAIR attributes held in a 32-bit MAIR register
10    #[bits(0..=7, rw)]
11    attrs: [u8; 4],
12}
13
14/// MAIR0 (*Memory Attribute Indirection Register 0*)
15#[derive(Debug, Copy, Clone)]
16#[cfg_attr(feature = "defmt", derive(defmt::Format))]
17#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
18pub struct Mair0;
19
20impl SysReg for Mair0 {
21    const CP: u32 = 15;
22    const CRN: u32 = 10;
23    const OP1: u32 = 0;
24    const CRM: u32 = 2;
25    const OP2: u32 = 0;
26}
27
28impl crate::register::SysRegRead for Mair0 {}
29
30impl Mair0 {
31    #[inline]
32    /// Reads MAIR0 (*Memory Attribute Indirection Register 0*)
33    pub fn read() -> Mair {
34        Mair::new_with_raw_value(<Self as SysRegRead>::read_raw())
35    }
36}
37
38impl crate::register::SysRegWrite for Mair0 {}
39
40impl Mair0 {
41    #[inline]
42    /// Writes MAIR0 (*Memory Attribute Indirection Register 0*)
43    ///
44    /// # Safety
45    ///
46    /// Ensure that this value is appropriate for this register
47    pub unsafe fn write(value: Mair) {
48        unsafe {
49            <Self as SysRegWrite>::write_raw(value.raw_value());
50        }
51    }
52}
aarch32_cpu/register/mair0.rs

aarch32_cpu/register/
mair0.rs
