aarch32_cpu/register/
ifsr.rs

1//! Code for managing IFSR (*Instruction Fault Status Register*)
2
3#[allow(unused)]
4use arbitrary_int::u4;
5
6use crate::register::{SysReg, SysRegRead, SysRegWrite};
7
8/// IFSR (*Instruction Fault Status Register*)
9#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
10#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
11#[cfg(arm_architecture = "v5te")]
12pub struct Ifsr {
13    /// Which domain was being accessed
14    #[bits(4..=7, rw)]
15    domain: u4,
16    /// Status
17    #[bits([0..=3], rw)]
18    status: Option<IfsrStatus>,
19}
20
21/// IFSR (*Instruction Fault Status Register*)
22#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
23#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
24#[cfg(arm_architecture = "v6")]
25pub struct Ifsr {
26    /// Which domain was being accessed
27    #[bits(4..=7, rw)]
28    domain: u4,
29    /// Status bitfield.
30    #[bits([0..=3], rw)]
31    status: Option<IfsrStatus>,
32}
33
34/// IFSR (*Instruction Fault Status Register*)
35#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
36#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
37#[cfg(arm_architecture = "v7-r")]
38pub struct Ifsr {
39    /// AXI Decode or Slave
40    #[bit(12, r)]
41    sd: bool,
42    /// Which domain was being accessed
43    #[bits(4..=7, rw)]
44    domain: u4,
45    /// Status bitfield.
46    #[bits([0..=3, 10], rw)]
47    status: Option<IfsrStatus>,
48}
49
50/// IFSR (*Instruction Fault Status Register*)
51#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
52#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
53#[cfg(arm_architecture = "v7-a")]
54pub struct Ifsr {
55    /// FAR not Valid
56    #[bit(16, rw)]
57    fnv: bool,
58    /// External Abort type
59    #[bit(12, rw)]
60    ext: bool,
61    /// Status bitfield.
62    #[bits([0..=3, 10], rw)]
63    status: Option<IfsrStatus>,
64}
65
66/// IFSR (*Instruction Fault Status Register*)
67#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
68#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
69#[cfg(arm_architecture = "v8-r")]
70pub struct Ifsr {
71    /// FAR not Valid
72    #[bit(16, rw)]
73    fnv: bool,
74    /// External Abort type
75    #[bit(12, rw)]
76    ext: bool,
77    /// Status bitfield.
78    #[bits([0..=5], rw)]
79    status: Option<IfsrStatus>,
80}
81
82/// Fault status register enumeration for IFSR
83#[bitbybit::bitenum(u4, exhaustive = false)]
84#[cfg_attr(feature = "defmt", derive(defmt::Format))]
85#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
86#[derive(Debug, PartialEq, Eq)]
87#[cfg(arm_architecture = "v5te")]
88pub enum IfsrStatus {
89    /// PC Alignment Fault
90    Alignment = 1,
91    /// Debug Exception
92    DebugEvent = 2,
93    /// Alternate value for PC Alignment Fault
94    AlignmentAlt = 3,
95    /// Translation fault, level 1
96    TranslationFaultFirstLevel = 5,
97    /// Translation fault, level 2
98    TranslationFaultSecondLevel = 7,
99    /// Synchronous External abort
100    SyncExtAbort = 8,
101    /// Domain fault, level 1
102    DomainFaultFirstLevel = 9,
103    /// Alternate value for Synchronous External abort
104    SyncExtAbortAlt = 10,
105    /// Domain fault, level 2
106    DomainFaultSecondLevel = 11,
107    /// Synchronous External abort, on translation table walk, level 1
108    SyncExtAbortOnTranslationTableWalkFirstLevel = 12,
109    /// Permission fault, level 1
110    PermissionFaultFirstLevel = 13,
111    /// Synchronous External abort, on translation table walk, level 2
112    SyncExtAbortOnTranslationTableWalkSecondLevel = 14,
113    /// Permission fault, level 2
114    PermissionFaultSecondLevel = 15,
115}
116
117/// Fault status register enumeration for IFSR
118#[bitbybit::bitenum(u4, exhaustive = false)]
119#[cfg_attr(feature = "defmt", derive(defmt::Format))]
120#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
121#[derive(Debug, PartialEq, Eq)]
122#[cfg(arm_architecture = "v6")]
123pub enum IfsrStatus {
124    /// PC Alignment Fault
125    Alignment = 1,
126    /// Debug Exception
127    DebugEvent = 2,
128    /// Access Flag fault, level 1
129    AccessFlagFaultFirstLevel = 3,
130    /// Translation fault, level 1
131    TranslationFaultFirstLevel = 5,
132    /// Access Flag fault, level 2
133    AccessFlagFaultSecondLevel = 6,
134    /// Translation fault, level 2
135    TranslationFaultSecondLevel = 7,
136    /// Synchronouse External Abort
137    SyncExtAbort = 8,
138    /// Domain fault, level 1
139    DomainFaultFirstLevel = 9,
140    /// Domain fault, level 2
141    DomainFaultSecondLevel = 11,
142    /// Synchronous External abort, on translation table walk, level 1
143    SyncExtAbortOnTranslationTableWalkFirstLevel = 12,
144    /// Permission fault, level 1
145    PermissionFaultFirstLevel = 13,
146    /// Synchronous External abort, on translation table walk, level 2
147    SyncExtAbortOnTranslationTableWalkSecondLevel = 14,
148    /// Permission fault, level 2
149    PermissionFaultSecondLevel = 15,
150}
151
152/// Fault status register enumeration for IFSR
153#[bitbybit::bitenum(u5, exhaustive = false)]
154#[cfg_attr(feature = "defmt", derive(defmt::Format))]
155#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
156#[derive(Debug, PartialEq, Eq)]
157#[cfg(arm_architecture = "v7-r")]
158pub enum IfsrStatus {
159    /// PC Alignment Fault
160    Alignment = 1,
161    /// Debug Exception
162    DebugEvent = 2,
163    /// Synchronous External abort
164    SyncExtAbort = 8,
165    /// Permission fault, level 1
166    PermissionFaultFirstLevel = 13,
167    /// Asynchronous External abort
168    AsyncExtAbort = 21,
169    /// Synchronous parity or ECC error
170    SyncParityEccError = 25,
171    /// asynchronous parity or ECC error
172    AsyncParityEccError = 24,
173}
174
175/// Fault status register enumeration for IFSR
176#[bitbybit::bitenum(u5, exhaustive = false)]
177#[cfg_attr(feature = "defmt", derive(defmt::Format))]
178#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
179#[derive(Debug, PartialEq, Eq)]
180#[cfg(arm_architecture = "v7-a")]
181pub enum IfsrStatus {
182    /// Synchronous External abort, on translation table walk, level 1
183    SyncExtAbortOnTranslationTableWalkFirstLevel = 0b01100,
184    /// Synchronous External abort, on translation table walk, level 2
185    SyncExtAbortOnTranslationTableWalkSecondLevel = 0b01110,
186    /// Synchronous parity or ECC error on memory access, on translation table walk, level 1
187    SyncParErrorOnTranslationTableWalkFirstLevel = 0b11100,
188    /// Synchronous parity or ECC error on memory access, on translation table walk, level 2
189    SyncParErrorOnTranslationTableWalkSecondLevel = 0b11110,
190    /// Translation fault, level 1
191    TranslationFaultFirstLevel = 0b00101,
192    /// Translation fault, level 2
193    TranslationFaultSecondLevel = 0b00111,
194    /// Access flag fault, level 1
195    AccessFlagFaultFirstLevel = 0b00011,
196    /// Access flag fault, level 2
197    AccessFlagFaultSecondLevel = 0b00110,
198    /// Domain fault, level 1
199    DomainFaultFirstLevel = 0b01001,
200    /// Domain fault, level 2
201    DomainFaultSecondLevel = 0b01011,
202    /// Permission fault, level 1
203    PermissionFaultFirstLevel = 0b01101,
204    /// Permission fault, level 2
205    PermissionFaultSecondLevel = 0b01111,
206    /// Debug exception
207    DebugEvent = 0b00010,
208    /// Synchronous External abort
209    SyncExtAbort = 0b01000,
210    /// TLB conflict abort
211    TlbConflictAbort = 0b10000,
212    /// IMPLEMENTATION DEFINED fault (Lockdown fault)
213    Lockdown = 0b10100,
214    /// Co-Processor Abort
215    CoprocessorAbort = 0b11010,
216    /// Synchronous parity or ECC error on memory access, not on translation table walk
217    SyncParErrorOnMemAccess = 0b11001,
218}
219
220/// Fault status register enumeration for IFSR
221#[bitbybit::bitenum(u6, exhaustive = false)]
222#[cfg_attr(feature = "defmt", derive(defmt::Format))]
223#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
224#[derive(Debug, PartialEq, Eq)]
225#[cfg(arm_architecture = "v8-r")]
226pub enum IfsrStatus {
227    /// Translation fault
228    Translation = 4,
229    /// Permission fault
230    Permission = 12,
231    /// Synchronous External abort
232    SyncExtAbort = 16,
233    /// Synchronous parity or ECC error on memory access
234    SyncParityEccError = 24,
235    /// PC alignment fault
236    PcAlignment = 33,
237    /// Debug exception
238    Debug = 34,
239}
240
241impl SysReg for Ifsr {
242    const CP: u32 = 15;
243    const CRN: u32 = 5;
244    const OP1: u32 = 0;
245    const CRM: u32 = 0;
246    const OP2: u32 = 1;
247}
248
249impl crate::register::SysRegRead for Ifsr {}
250
251impl Ifsr {
252    #[inline]
253    /// Reads IFSR (*Instruction Fault Status Register*)
254    pub fn read() -> Ifsr {
255        Self::new_with_raw_value(<Self as SysRegRead>::read_raw())
256    }
257}
258
259impl crate::register::SysRegWrite for Ifsr {}
260
261impl Ifsr {
262    #[inline]
263    /// Writes IFSR (*Instruction Fault Status Register*)
264    ///
265    /// # Safety
266    ///
267    /// Ensure that this value is appropriate for this register
268    pub unsafe fn write(value: Self) {
269        unsafe {
270            <Self as SysRegWrite>::write_raw(value.raw_value());
271        }
272    }
273}
aarch32_cpu/register/ifsr.rs

aarch32_cpu/register/
ifsr.rs
