aarch32_cpu/register/
iciallu.rs

1//! Code for managing ICIALLU (*Invalidate entire instruction cache to PoU Register*)
2//!
3//! Starting with ARMv6, the type of cache can be determined from the System Coprocessor register 0,
4//! and controlled through registers 1, 7 and 9. In earlier architecture variants, it is
5//! IMPLEMENTATION DEFINED whether this instruction is supported.
6use crate::register::{SysReg, SysRegWrite};
7
8#[derive(Debug, Copy, Clone)]
9#[cfg_attr(feature = "defmt", derive(defmt::Format))]
10#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
11/// ICIALLU (*Invalidate entire instruction cache to PoU Register*)
12pub struct Iciallu;
13
14impl SysReg for Iciallu {
15    const CP: u32 = 15;
16    const CRN: u32 = 7;
17    const OP1: u32 = 0;
18    const CRM: u32 = 5;
19    const OP2: u32 = 0;
20}
21
22impl crate::register::SysRegWrite for Iciallu {}
23
24impl Iciallu {
25    #[inline]
26    /// Writes 0 to ICIALLU (*Invalidate entire instruction cache to PoU Register*) to trigger operation
27    pub fn write() {
28        unsafe {
29            <Self as SysRegWrite>::write_raw(0);
30        }
31    }
32}
aarch32_cpu/register/iciallu.rs

aarch32_cpu/register/
iciallu.rs
