aarch32_cpu/register/hyp/
hvbar.rs

1//! Code for managing HVBAR (*Hyp Vector Base Address Register*)
2
3use crate::register::{SysReg, SysRegRead, SysRegWrite};
4
5/// HVBAR (*Hyp Vector Base Address Register*)
6///
7/// There is no `modify` method because this register holds a single 32-bit address.
8///
9/// This is only available in EL2.
10#[derive(Debug, Clone, Copy, PartialEq, Eq)]
11#[repr(transparent)]
12#[cfg_attr(feature = "defmt", derive(defmt::Format))]
13#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
14pub struct Hvbar(pub u32);
15
16impl SysReg for Hvbar {
17    const CP: u32 = 15;
18    const CRN: u32 = 12;
19    const OP1: u32 = 4;
20    const CRM: u32 = 0;
21    const OP2: u32 = 0;
22}
23
24impl SysRegRead for Hvbar {}
25
26impl SysRegWrite for Hvbar {}
27
28impl Hvbar {
29    /// Read HVBAR (*Hyp Vector Base Address Register*)
30    #[inline]
31    pub fn read() -> Hvbar {
32        Self(<Self as SysRegRead>::read_raw())
33    }
34
35    /// Write HVBAR (*Hyp Vector Base Address Register*)
36    ///
37    /// # Safety
38    ///
39    /// You must supply a correctly-aligned address of a valid Arm AArch32
40    /// Vector Table.
41    #[inline]
42    pub unsafe fn write(value: Self) {
43        // Safety: Writing this register is atomic
44        unsafe {
45            <Self as SysRegWrite>::write_raw(value.0);
46        }
47    }
48}
aarch32_cpu/register/hyp/hvbar.rs

aarch32_cpu/register/hyp/
hvbar.rs
