aarch32_cpu/register/hyp/
hcr.rs

1//! Code for managing HCR (*Hyp Configuration Register*)
2
3use crate::register::{SysReg, SysRegRead, SysRegWrite};
4
5/// HCR (*Hyp Configuration Register*)
6#[bitbybit::bitfield(u32, debug, defmt_fields(feature = "defmt"))]
7#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
8pub struct Hcr {
9    /// TCPAC - Traps EL1 accesses to the CPACR to Hyp mode
10    #[bit(31, rw)]
11    tcpac: bool,
12    /// TRVM - Trap Reads of Memory controls
13    #[bit(30, rw)]
14    trvm: bool,
15    /// HCD - HVC instruction disable
16    #[bit(29, rw)]
17    hcd: bool,
18    /// TGE - Trap General Exceptions from EL0
19    #[bit(27, rw)]
20    tge: bool,
21    /// TVM - Trap Memory controls
22    #[bit(26, rw)]
23    tvm: bool,
24    /// TPU - Trap cache maintenance instructions that operate to the Point of Unification
25    #[bit(24, rw)]
26    tpu: bool,
27    /// TPC - Trap data or unified cache maintenance instructions that operate to the Point of Coherency
28    #[bit(23, rw)]
29    tpc: bool,
30    /// TSW - Trap data or unified cache maintenance instructions that operate by Set/Way
31    #[bit(22, rw)]
32    tsw: bool,
33    /// TAC - Trap Auxiliary Control Registers
34    #[bit(21, rw)]
35    tac: bool,
36    /// TIDCP - Trap IMPLEMENTATION DEFINED functionality
37    #[bit(20, rw)]
38    tidcp: bool,
39    /// TID3 - Trap ID group 3
40    #[bit(18, rw)]
41    tid3: bool,
42    /// TID2 - Trap ID group 2
43    #[bit(17, rw)]
44    tid2: bool,
45    /// TID1 - Trap ID group 1
46    #[bit(16, rw)]
47    tid1: bool,
48    /// TID0 - Trap ID group 0
49    #[bit(15, rw)]
50    tid0: bool,
51    /// TWE - Traps EL0 and EL1 execution of WFE instructions to Hyp mode
52    #[bit(14, rw)]
53    twe: bool,
54    /// TWI - Traps EL0 and EL1 execution of WFI instructions to Hyp mode
55    #[bit(13, rw)]
56    twi: bool,
57    /// DC - Default Cacheability
58    #[bit(12, rw)]
59    dc: bool,
60    /// BSU - Barrier Shareability upgrade.
61    #[bits(10..=11, rw)]
62    bsu: Bsu,
63    /// FB - Force broadcast
64    #[bit(9, rw)]
65    fb: bool,
66    /// VA - Virtual SError interrupt exception
67    #[bit(8, rw)]
68    va: bool,
69    /// VI - Virtual IRQ exception
70    #[bit(7, rw)]
71    vi: bool,
72    /// VF - Virtual FIQ exception
73    #[bit(6, rw)]
74    vf: bool,
75    /// AMO - SError interrupt Mask Override
76    #[bit(5, rw)]
77    amo: bool,
78    /// IMO - IRQ Mask Override
79    #[bit(4, rw)]
80    imo: bool,
81    /// FMO - FIQ Mask Override
82    #[bit(3, rw)]
83    fmo: bool,
84    /// SWIO - Set/Way Invalidation Override
85    #[bit(1, rw)]
86    swio: bool,
87    /// VM - Virtualization enable
88    #[bit(0, rw)]
89    vm: bool,
90}
91
92/// Barrier Shareability upgrade
93///
94/// This field determines the minimum Shareability domain that is applied to any
95/// barrier instruction executed from EL1 or EL0
96#[bitbybit::bitenum(u2, exhaustive = true)]
97#[cfg_attr(feature = "defmt", derive(defmt::Format))]
98#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
99#[derive(Debug, PartialEq, Eq)]
100pub enum Bsu {
101    /// No effect
102    NoEffect = 0b00,
103    /// Inner Shareable
104    InnerShareable = 0b01,
105    /// Outer Shareable
106    OuterShareable = 0b10,
107    /// Full System
108    FullSystem = 0b11,
109}
110
111impl SysReg for Hcr {
112    const CP: u32 = 15;
113    const CRN: u32 = 1;
114    const OP1: u32 = 4;
115    const CRM: u32 = 1;
116    const OP2: u32 = 0;
117}
118
119impl crate::register::SysRegRead for Hcr {}
120
121impl Hcr {
122    #[inline]
123    /// Reads HCR (*Hyp Configuration Register*)
124    pub fn read() -> Hcr {
125        Self::new_with_raw_value(<Self as SysRegRead>::read_raw())
126    }
127}
128
129impl crate::register::SysRegWrite for Hcr {}
130
131impl Hcr {
132    #[inline]
133    /// Writes HCR (*Hyp Configuration Register*)
134    pub fn write(value: Self) {
135        unsafe {
136            <Self as SysRegWrite>::write_raw(value.raw_value());
137        }
138    }
139
140    #[inline]
141    /// Modify HCR (*Hyp Configuration Register*)
142    pub fn modify<F>(f: F)
143    where
144        F: FnOnce(&mut Self),
145    {
146        let mut value = Self::read();
147        f(&mut value);
148        Self::write(value);
149    }
150}
aarch32_cpu/register/hyp/hcr.rs

aarch32_cpu/register/hyp/
hcr.rs
