aarch32_cpu/register/hyp/
hcptr.rs

1//! Code for managing HCPTR (*Hyp Architectural Feature Trap Register*)
2
3use crate::register::{SysReg, SysRegRead, SysRegWrite};
4
5/// HCPTR (*Hyp Architectural Feature Trap Register*)
6#[bitbybit::bitfield(u32, debug, defmt_fields(feature = "defmt"))]
7#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
8pub struct Hcptr {
9    /// TCPAC - Traps EL1 accesses to the CPACR to Hyp mode
10    #[bit(31, rw)]
11    tcpac: bool,
12    /// TTA - Traps System register accesses to all implemented trace registers to Hyp mode
13    #[bit(20, rw)]
14    tta: bool,
15    /// TASE - Traps execution of Advanced SIMD instructions to Hyp mode when the value of HCPTR.TCP10 is 0.
16    #[bit(15, rw)]
17    tase: bool,
18    /// TCP - Trap accesses to Advanced SIMD and floating-point functionality to Hyp mode
19    #[bit(10, rw)]
20    tcp: bool,
21}
22
23impl SysReg for Hcptr {
24    const CP: u32 = 15;
25    const CRN: u32 = 1;
26    const OP1: u32 = 4;
27    const CRM: u32 = 1;
28    const OP2: u32 = 2;
29}
30
31impl crate::register::SysRegRead for Hcptr {}
32
33impl Hcptr {
34    #[inline]
35    /// Reads HCPTR (*Hyp Architectural Feature Trap Register*)
36    pub fn read() -> Hcptr {
37        Self::new_with_raw_value(<Self as SysRegRead>::read_raw())
38    }
39
40    /// Modify HCPTR (*Hyp Architectural Feature Trap Register*)
41    #[inline]
42    pub fn modify<F>(f: F)
43    where
44        F: FnOnce(&mut Self),
45    {
46        let mut value = Self::read();
47        f(&mut value);
48        Self::write(value);
49    }
50}
51
52impl crate::register::SysRegWrite for Hcptr {}
53
54impl Hcptr {
55    #[inline]
56    /// Writes HCPTR (*Hyp Architectural Feature Trap Register*)
57    pub fn write(value: Self) {
58        unsafe {
59            <Self as SysRegWrite>::write_raw(value.raw_value());
60        }
61    }
62}
aarch32_cpu/register/hyp/hcptr.rs

aarch32_cpu/register/hyp/
hcptr.rs
