aarch32_cpu/register/generic_timer/
cnthctl.rs

1//! Code for managing CNTHCTL (*Hyp Counter-timer Control Register*)
2
3use arbitrary_int::u4;
4
5use crate::register::{SysReg, SysRegRead, SysRegWrite};
6
7/// CNTHCTL (*Hyp Counter-timer Control Register*)
8#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
9#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
10pub struct Cnthctl {
11    /// Selects which bit of CNTPCT, as seen from EL2, is the trigger for the
12    /// event stream generated from that counter when that stream is enabled.
13    #[bits(4..=7, rw)]
14    evnti: u4,
15    /// Controls which transition of the CNTPCT trigger bit, as seen from EL2
16    /// and defined by EVNTI, generates an event when the event stream is
17    /// enabled.
18    #[bits(3..=3, rw)]
19    evntdir: bool,
20    /// Enables the generation of an event stream from CNTPCT as seen from EL2.
21    #[bits(2..=2, rw)]
22    evnten: bool,
23    /// Traps Non-secure EL0 and EL1 MRC or MCR accesses, reported using EC
24    /// syndrome value 0x03, and MRRC or MCRR accesses, reported using EC
25    /// syndrome value 0x04, to the physical timer registers to Hyp mode.
26    #[bits(1..=1, rw)]
27    pl1pcen: bool,
28    /// Traps Non-secure EL0 and EL1 MRRC or MCRR accesses, reported using EC
29    /// syndrome value 0x04, to the physical counter register to Hyp mode.
30    #[bits(0..=0, rw)]
31    pl1pcten: bool,
32}
33
34impl SysReg for Cnthctl {
35    const CP: u32 = 15;
36    const CRN: u32 = 14;
37    const OP1: u32 = 4;
38    const CRM: u32 = 1;
39    const OP2: u32 = 0;
40}
41
42impl SysRegRead for Cnthctl {}
43
44impl Cnthctl {
45    #[inline]
46    /// Reads CNTHCTL (*Hyp Counter-timer Control Register*)
47    pub fn read() -> Cnthctl {
48        Self::new_with_raw_value(<Self as SysRegRead>::read_raw())
49    }
50}
51
52impl SysRegWrite for Cnthctl {}
53
54impl Cnthctl {
55    #[inline]
56    /// Writes CNTHCTL (*Hyp Counter-timer Control Register*)
57    pub fn write(value: Self) {
58        unsafe {
59            <Self as SysRegWrite>::write_raw(value.raw_value());
60        }
61    }
62}
aarch32_cpu/register/generic_timer/cnthctl.rs

aarch32_cpu/register/generic_timer/
cnthctl.rs
