aarch32_cpu/register/
dcisw.rs

1//! Code for managing DCISW (*Data Cache line Invalidate by Set/Way Register*)
2
3use arbitrary_int::u3;
4
5use crate::register::{SysReg, SysRegWrite};
6
7#[derive(Debug, Copy, Clone)]
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
10/// DCISW (*Data Cache line Invalidate by Set/Way Register*)
11pub struct Dcisw(pub u32);
12
13impl Dcisw {
14    /// Create DCISW value for cache invalidation by set and way.
15    ///
16    /// ## Generics
17    ///
18    /// - A: log2(ASSOCIATIVITY) rounded up to the next integer if necessary. For example, a 4-way
19    ///   associative cache will have a value of 2 and a 8-way associative cache will have a value of
20    ///   3.
21    /// - N: log2(LINE LENGTH). For example, a 32-byte line length (4 words) will have a value of
22    ///   5.
23    #[inline]
24    pub const fn new<const A: usize, const N: usize>(way: u8, set: u16, level: u3) -> Self {
25        Self(super::dc_sw_ops::new::<A, N>(way, set, level))
26    }
27
28    /// Create DCISW value for cache invalidation by set and way.
29    /// Returns [None] on invalid input.
30    ///
31    /// # Arguments
32    ///
33    /// - a: log2(ASSOCIATIVITY) rounded up to the next integer if necessary. For example, a 4-way
34    ///   associative cache will have a value of 2 and a 8-way associative cache will have a value of
35    ///   3.
36    /// - n: log2(LINE LENGTH). For example, a 32-byte line length (4 words) will have a value of
37    ///   5.
38    #[inline]
39    pub const fn new_with_offsets(a: usize, way: u8, n: usize, set: u16, level: u3) -> Self {
40        Self(super::dc_sw_ops::new_with_offsets(a, way, n, set, level))
41    }
42}
43
44impl SysReg for Dcisw {
45    const CP: u32 = 15;
46    const CRN: u32 = 7;
47    const OP1: u32 = 0;
48    const CRM: u32 = 6;
49    const OP2: u32 = 2;
50}
51
52impl crate::register::SysRegWrite for Dcisw {}
53
54impl Dcisw {
55    #[inline]
56    /// Writes DCSW (*Data Cache line Invalidate by Set/Way Register*)
57    ///
58    /// # Safety
59    ///
60    /// Ensure that this value is appropriate for this register
61    pub unsafe fn write(value: Self) {
62        unsafe {
63            <Self as SysRegWrite>::write_raw(value.0);
64        }
65    }
66}
aarch32_cpu/register/dcisw.rs

aarch32_cpu/register/
dcisw.rs
