aarch32_cpu/register/
dcimvac.rs

1//! Code for managing DCIMVAC (*Data Cache line Invalidate by VA to PoC Register*)
2
3use crate::register::{SysReg, SysRegWrite};
4
5#[derive(Debug, Copy, Clone)]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
8/// DCIMVAC (*Data Cache line Invalidate by VA to PoC Register*)
9pub struct Dcimvac(pub u32);
10
11impl Dcimvac {
12    #[inline]
13    /// Create a new DCIMVAC value, given an address
14    pub const fn new(addr: u32) -> Self {
15        Self(addr)
16    }
17}
18
19impl SysReg for Dcimvac {
20    const CP: u32 = 15;
21    const CRN: u32 = 7;
22    const OP1: u32 = 0;
23    const CRM: u32 = 6;
24    const OP2: u32 = 1;
25}
26
27impl crate::register::SysRegWrite for Dcimvac {}
28
29impl Dcimvac {
30    #[inline]
31    /// Writes DCIMVAC (*Data Cache line Invalidate by VA to PoC Register*)
32    ///
33    /// # Safety
34    ///
35    /// Ensure that this value is appropriate for this register. Generally, the address passed
36    /// to the write call should be aligned to the cache line size.
37    pub unsafe fn write(value: Self) {
38        unsafe {
39            <Self as SysRegWrite>::write_raw(value.0);
40        }
41    }
42}
aarch32_cpu/register/dcimvac.rs

aarch32_cpu/register/
dcimvac.rs
