aarch32_cpu/register/
dccmvau.rs

1//! Code for managing DCCMVAU (*Data Cache line Clean by VA to PoU Register*)
2
3use crate::register::{SysReg, SysRegWrite};
4
5#[derive(Debug, Copy, Clone)]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
8/// DCCMVAU (*Data Cache line Clean by VA to PoU Register*)
9pub struct Dccmvau(pub u32);
10
11impl Dccmvau {
12    #[inline]
13    /// Create a new DCCMVAU value containing the Virtual Address to clean
14    pub const fn new(addr: u32) -> Self {
15        Self(addr)
16    }
17}
18
19impl SysReg for Dccmvau {
20    const CP: u32 = 15;
21    const CRN: u32 = 7;
22    const OP1: u32 = 0;
23    const CRM: u32 = 11;
24    const OP2: u32 = 1;
25}
26
27impl crate::register::SysRegWrite for Dccmvau {}
28
29impl Dccmvau {
30    #[inline]
31    /// Writes DCCMVAU (*Data Cache line Clean by VA to PoU Register*)
32    ///
33    /// # Safety
34    ///
35    /// Ensure that this value is appropriate for this register. Generally, the address passed
36    /// to the write call should be aligned to the cache line size.
37    pub unsafe fn write(value: Self) {
38        unsafe {
39            <Self as SysRegWrite>::write_raw(value.0);
40        }
41    }
42}
aarch32_cpu/register/dccmvau.rs

aarch32_cpu/register/
dccmvau.rs
