aarch32_cpu/register/
dacr.rs

1//! Code for managing DACR (*Domain Access Control Register*)
2
3use crate::register::{SysReg, SysRegRead, SysRegWrite};
4
5/// DACR (*Domain Access Control Register*)
6#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
7#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
8pub struct Dacr {
9    /// An array of bits controlling access to each of the 16 domains
10    #[bits(0..=1, rw)]
11    d: [DomainAccess; 16],
12}
13
14/// Domain Access Permissions
15#[derive(Debug)]
16#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
17#[cfg_attr(feature = "defmt", derive(defmt::Format))]
18#[bitbybit::bitenum(u2, exhaustive = true)]
19pub enum DomainAccess {
20    /// No access. Any access to the domain generates a Domain fault.
21    NoAccess = 0b00,
22    /// Cient. Accesses are checked against the permission bits in the translation tables.
23    Client = 0b01,
24    /// Reserved
25    Reserved = 0b10,
26    /// Manager. Accesses are not checked against the permission bits in the translation tables.
27    Manager = 0b11,
28}
29
30impl SysReg for Dacr {
31    const CP: u32 = 15;
32    const CRN: u32 = 3;
33    const OP1: u32 = 0;
34    const CRM: u32 = 0;
35    const OP2: u32 = 0;
36}
37
38impl crate::register::SysRegRead for Dacr {}
39
40impl Dacr {
41    #[inline]
42    /// Reads DACR (*Domain Access Control Register*)
43    pub fn read() -> Dacr {
44        Self::new_with_raw_value(<Self as SysRegRead>::read_raw())
45    }
46}
47
48impl crate::register::SysRegWrite for Dacr {}
49
50impl Dacr {
51    #[inline]
52    /// Writes DACR (*Domain Access Control Register*)
53    pub fn write(value: Self) {
54        unsafe {
55            <Self as SysRegWrite>::write_raw(value.raw_value());
56        }
57    }
58
59    /// Modify DACR (*Domain Access Control Register*)
60    #[inline]
61    pub fn modify<F>(f: F)
62    where
63        F: FnOnce(&mut Self),
64    {
65        let mut value = Self::read();
66        f(&mut value);
67        Self::write(value);
68    }
69}
aarch32_cpu/register/dacr.rs

aarch32_cpu/register/
dacr.rs
