aarch32_cpu/register/
csselr.rs

1//! Code for managing CSSELR (*Cache Size Selection Register*)
2use arbitrary_int::u3;
3
4use crate::register::{SysReg, SysRegRead, SysRegWrite};
5
6#[bitbybit::bitenum(u1, exhaustive = true)]
7#[derive(Debug, PartialEq, Eq)]
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
10/// Type of processor cache
11pub enum CacheType {
12    /// Data or Unified Cache
13    DataOrUnified = 0,
14    /// Instruction Cache
15    Instruction = 1,
16}
17
18/// CSSELR (*Cache Size Selection Register*)
19#[bitbybit::bitfield(u32, debug, defmt_fields(feature = "defmt"))]
20#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
21#[derive(PartialEq, Eq)]
22pub struct Csselr {
23    /// 0 for L1 cache, 1 for L2, etc.
24    #[bits(1..=3, rw)]
25    level: u3,
26    /// The type of cache
27    #[bit(0, rw)]
28    cache_type: CacheType,
29}
30
31impl SysReg for Csselr {
32    const CP: u32 = 15;
33    const CRN: u32 = 0;
34    const OP1: u32 = 2;
35    const CRM: u32 = 0;
36    const OP2: u32 = 0;
37}
38
39impl crate::register::SysRegRead for Csselr {}
40
41impl Csselr {
42    #[inline]
43    /// Reads CSSELR (*Cache Size Selection Register*)
44    pub fn read() -> Csselr {
45        Self::new_with_raw_value(<Self as SysRegRead>::read_raw())
46    }
47}
48
49impl crate::register::SysRegWrite for Csselr {}
50
51impl Csselr {
52    #[inline]
53    /// Writes CSSELR (*Cache Size Selection Register*)
54    ///
55    /// # Safety
56    ///
57    /// Ensure that this value is appropriate for this register
58    pub unsafe fn write(value: Self) {
59        unsafe {
60            <Self as SysRegWrite>::write_raw(value.raw_value());
61        }
62    }
63}
aarch32_cpu/register/csselr.rs

aarch32_cpu/register/
csselr.rs
