aarch32_cpu/register/
ccsidr.rs

1//! Code for managing CCSIDR (*Current Cache Size ID Register*)
2
3use crate::register::{SysReg, SysRegRead};
4use arbitrary_int::{u10, u15, u3};
5
6/// CCSIDR (*Current Cache Size ID Register*)
7#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
8#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
9pub struct Ccsidr {
10    /// Indicates whether the cache level supports Write-Through
11    #[bit(31, rw)]
12    write_through: bool,
13    /// Indicates whether the cache level supports Write-Back
14    #[bit(30, rw)]
15    write_back: bool,
16    /// Indicates whether the cache level supports Read-Allocation
17    #[bit(29, rw)]
18    read_alloc: bool,
19    /// Indicates whether the cache level supports Write-Allocation
20    #[bit(28, rw)]
21    write_alloc: bool,
22    /// Number of sets in cache, minus 1
23    #[bits(13..=27, rw)]
24    num_sets: u15,
25    /// Associativity of cache, minus 1
26    #[bits(3..=12, rw)]
27    associativity: u10,
28    /// log2(cache line size in words), minus 1
29    #[bits(0..=2, rw)]
30    line_size: u3,
31}
32
33impl SysReg for Ccsidr {
34    const CP: u32 = 15;
35    const CRN: u32 = 0;
36    const OP1: u32 = 1;
37    const CRM: u32 = 0;
38    const OP2: u32 = 0;
39}
40
41impl crate::register::SysRegRead for Ccsidr {}
42
43impl Ccsidr {
44    #[inline]
45    /// Reads CCSIDR (*Current Cache Size ID Register*)
46    pub fn read() -> Ccsidr {
47        Self::new_with_raw_value(<Self as SysRegRead>::read_raw())
48    }
49}
aarch32_cpu/register/ccsidr.rs

aarch32_cpu/register/
ccsidr.rs
