aarch32_cpu/register/
midr.rs

1//! Code for managing MIDR (*Main ID Register*)
2
3use arbitrary_int::{u12, u4};
4
5use super::{SysReg, SysRegRead};
6
7/// MIDR (*Main ID Register*)
8#[bitbybit::bitfield(u32)]
9pub struct Midr {
10    /// Implementer
11    #[bits(24..=31, r)]
12    implementer: u8,
13    /// Variant
14    #[bits(20..=23, r)]
15    variant: u4,
16    /// Architecture
17    #[bits(16..=19, r)]
18    arch: u4,
19    /// Part Number
20    #[bits(4..=15, r)]
21    part_no: u12,
22    /// Revision
23    #[bits(0..=3, r)]
24    rev: u4,
25}
26
27impl SysReg for Midr {
28    const CP: u32 = 15;
29    const CRN: u32 = 0;
30    const OP1: u32 = 0;
31    const CRM: u32 = 0;
32    const OP2: u32 = 0;
33}
34
35impl SysRegRead for Midr {}
36
37impl Midr {
38    /// Read MIDR (*Main ID Register*)
39    #[inline]
40    pub fn read() -> Midr {
41        // Safety: Reading this register has no side-effects and is atomic
42        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
43    }
44}
45
46impl core::fmt::Debug for Midr {
47    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
48        write!(f, "MIDR {{ implementer=0x{:02x} variant=0x{:x} arch=0x{:x} part_no=0x{:03x} rev=0x{:x} }}",
49        self.implementer(), self.variant(), self.arch(), self.part_no(), self.rev())
50    }
51}
52
53#[cfg(feature = "defmt")]
54impl defmt::Format for Midr {
55    fn format(&self, f: defmt::Formatter) {
56        defmt::write!(f, "MIDR {{ implementer=0x{0=24..32:02x} variant=0x{0=20..24:x} arch=0x{0=16..20:x} part_no=0x{0=4..16:03x} rev=0x{0=0..4:x} }}", self.raw_value())
57    }
58}
aarch32_cpu/register/midr.rs

aarch32_cpu/register/
midr.rs
