aarch32_cpu/register/
irsr.rs

1//! Code for managing IRSR (*Instruction Region Size and Enable Register*)
2
3use crate::register::{SysReg, SysRegRead, SysRegWrite};
4
5pub use super::drsr::RegionSize;
6
7/// IRSR (*Instruction Region Size and Enable Register*)
8#[bitbybit::bitfield(u32, debug, defmt_fields(feature = "defmt"))]
9#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
10pub struct Irsr {
11    /// Sub-region bitmask
12    ///
13    /// The region is divided into exactly eight equal sized subregions.
14    /// Subregion 0 is the subregion at the least significant address.
15    ///
16    /// A 1 bit means that sub-region is disabled.
17    ///
18    /// Only applies to regions sized 256 bytes or larger.
19    #[bits(8..=15, rw)]
20    subregion_mask: u8,
21    /// Region Size
22    #[bits(1..=5, rw)]
23    region_size: RegionSize,
24    /// Is region enabled?
25    #[bits(0..=0, rw)]
26    enabled: bool,
27}
28
29impl SysReg for Irsr {
30    const CP: u32 = 15;
31    const CRN: u32 = 6;
32    const OP1: u32 = 0;
33    const CRM: u32 = 1;
34    const OP2: u32 = 3;
35}
36
37impl crate::register::SysRegRead for Irsr {}
38
39impl Irsr {
40    #[inline]
41    /// Reads IRSR (*Instruction Region Size and Enable Register*)
42    ///
43    /// Set RGNR to control which region this reads.
44    pub fn read() -> Irsr {
45        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
46    }
47}
48
49impl crate::register::SysRegWrite for Irsr {}
50
51impl Irsr {
52    #[inline]
53    /// Writes IRSR (*Instruction Region Size and Enable Register*)
54    ///
55    /// Set RGNR to control which region this affects.
56    pub fn write(value: Irsr) {
57        unsafe { <Self as SysRegWrite>::write_raw(value.raw_value()) }
58    }
59}
aarch32_cpu/register/irsr.rs

aarch32_cpu/register/
irsr.rs
