aarch32_cpu/register/
iracr.rs

1//! Code for managing IRACR (*Instruction Region Access Control Register*)
2
3use arbitrary_int::u3;
4
5use crate::register::{SysReg, SysRegRead, SysRegWrite};
6
7/// IRACR (*Instruction Region Access Control Register*)
8#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
9#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
10pub struct Iracr {
11    /// Execute Never
12    #[bits(12..=12, rw)]
13    nx: bool,
14    /// Access Permission bits
15    #[bits(8..=10, rw)]
16    ap: u3,
17    /// TEX bits
18    #[bits(3..=5, rw)]
19    tex: u3,
20    /// S bit
21    #[bits(2..=2, rw)]
22    s: bool,
23    /// C bit
24    #[bits(1..=1, rw)]
25    c: bool,
26    /// B bit
27    #[bits(0..=0, rw)]
28    b: bool,
29}
30
31impl SysReg for Iracr {
32    const CP: u32 = 15;
33    const CRN: u32 = 6;
34    const OP1: u32 = 0;
35    const CRM: u32 = 1;
36    const OP2: u32 = 5;
37}
38
39impl crate::register::SysRegRead for Iracr {}
40
41impl Iracr {
42    #[inline]
43    /// Reads IRACR (*Instruction Region Access Control Register*)
44    ///
45    /// Set RGNR to control which region this reads.
46    pub fn read() -> Iracr {
47        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
48    }
49}
50
51impl crate::register::SysRegWrite for Iracr {}
52
53impl Iracr {
54    #[inline]
55    /// Writes IRACR (*Instruction Region Access Control Register*)
56    ///
57    /// Set RGNR to control which region this affects.
58    pub fn write(value: Iracr) {
59        unsafe { <Self as SysRegWrite>::write_raw(value.raw_value()) }
60    }
61}
aarch32_cpu/register/iracr.rs

aarch32_cpu/register/
iracr.rs
