aarch32_cpu/register/
dccimvac.rs

1//! DCCIMVAC (*Clean And Invalidate Data Cache Or Unified Cache Line by MVA to Point of Coherence.*)
2use crate::register::{SysReg, SysRegWrite};
3
4#[derive(Debug, Copy, Clone)]
5#[cfg_attr(feature = "defmt", derive(defmt::Format))]
6#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
7pub struct Dccimvac(pub u32);
8
9impl Dccimvac {
10    #[inline]
11    pub const fn new(addr: u32) -> Self {
12        Self(addr)
13    }
14}
15
16impl SysReg for Dccimvac {
17    const CP: u32 = 15;
18    const CRN: u32 = 7;
19    const OP1: u32 = 0;
20    const CRM: u32 = 14;
21    const OP2: u32 = 1;
22}
23
24impl crate::register::SysRegWrite for Dccimvac {}
25
26impl Dccimvac {
27    #[inline]
28    /// Writes DCCIMVAC (*Clean And Invalidate Data Cache Or Unified Cache Line by MVA to Point of Coherence.*)
29    ///
30    /// # Safety
31    ///
32    /// Ensure that this value is appropriate for this register. Generally, the address passed
33    /// to the write call should be aligned to the cache line size.
34    pub unsafe fn write(value: Self) {
35        unsafe {
36            <Self as SysRegWrite>::write_raw(value.0);
37        }
38    }
39}
aarch32_cpu/register/dccimvac.rs

aarch32_cpu/register/
dccimvac.rs
