aarch32_cpu/register/armv8r/
vbar.rs

1//! Code for managing VBAR (*Vector Base Address Register*)
2
3use crate::register::{SysReg, SysRegRead, SysRegWrite};
4
5/// VBAR (*Vector Base Address Register*)
6///
7/// There is no `modify` method because this register holds a single 32-bit address.
8#[derive(Debug, Clone, Copy, PartialEq, Eq)]
9#[repr(transparent)]
10#[cfg_attr(feature = "defmt", derive(defmt::Format))]
11#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
12pub struct Vbar(pub u32);
13
14impl SysReg for Vbar {
15    const CP: u32 = 15;
16    const CRN: u32 = 12;
17    const OP1: u32 = 0;
18    const CRM: u32 = 0;
19    const OP2: u32 = 0;
20}
21
22impl SysRegRead for Vbar {}
23
24impl SysRegWrite for Vbar {}
25
26impl Vbar {
27    /// Read VBAR (*Vector Base Address Register*)
28    #[inline]
29    pub fn read() -> Vbar {
30        // Safety: Reading this register has no side-effects and is atomic
31        unsafe { Self(<Self as SysRegRead>::read_raw()) }
32    }
33
34    /// Write VBAR (*Vector Base Address Register*)
35    ///
36    /// # Safety
37    ///
38    /// You must supply a correctly-aligned address of a valid Arm AArch32
39    /// Vector Table.
40    #[inline]
41    pub unsafe fn write(value: Self) {
42        // Safety: Writing this register is atomic
43        unsafe {
44            <Self as SysRegWrite>::write_raw(value.0 as u32);
45        }
46    }
47}
aarch32_cpu/register/armv8r/vbar.rs

aarch32_cpu/register/armv8r/
vbar.rs
