aarch32_cpu/register/armv8r/
prlar2.rs

1//! Code for managing PRLAR2 (*Protection Region Limit Address Register 2*)
2
3use crate::register::{SysReg, SysRegRead, SysRegWrite};
4
5/// PRLAR2 (*Protection Region Limit Address Register 2*)
6#[derive(Debug, Clone, Copy)]
7#[cfg_attr(feature = "defmt", derive(defmt::Format))]
8#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
9pub struct Prlar2(pub u32);
10
11impl SysReg for Prlar2 {
12    const CP: u32 = 15;
13    const CRN: u32 = 6;
14    const OP1: u32 = 0;
15    const CRM: u32 = 9;
16    const OP2: u32 = 1;
17}
18
19impl crate::register::SysRegRead for Prlar2 {}
20
21impl Prlar2 {
22    #[inline]
23    /// Reads PRLAR2 (*Protection Region Limit Address Register 2*)
24    pub fn read() -> Prlar2 {
25        unsafe { Self(<Self as SysRegRead>::read_raw()) }
26    }
27}
28
29impl crate::register::SysRegWrite for Prlar2 {}
30
31impl Prlar2 {
32    #[inline]
33    /// Writes PRLAR2 (*Protection Region Limit Address Register 2*)
34    ///
35    /// # Safety
36    ///
37    /// Ensure that this value is appropriate for this register
38    pub unsafe fn write(value: Self) {
39        unsafe {
40            <Self as SysRegWrite>::write_raw(value.0);
41        }
42    }
43}
aarch32_cpu/register/armv8r/prlar2.rs

aarch32_cpu/register/armv8r/
prlar2.rs
