aarch32_cpu/register/armv8r/
prbar.rs

1//! Code for managing PRBAR (*Protection Region Base Address Register*)
2
3use arbitrary_int::u26;
4
5use crate::register::{SysReg, SysRegRead, SysRegWrite};
6
7/// Shareability for an MPU Region
8#[derive(Debug, PartialEq, Eq)]
9#[cfg_attr(feature = "defmt", derive(defmt::Format))]
10#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
11#[bitbybit::bitenum(u2, exhaustive = true)]
12pub enum Shareability {
13    /// Non-shareable
14    NonShareable = 0b00,
15    /// Reserved
16    Reserved = 0b01,
17    /// Outer-Shareable
18    OuterShareable = 0b10,
19    /// Inner-Shareable
20    InnerShareable = 0b11,
21}
22
23/// Access Permissions for an MPU Region
24#[derive(Debug, PartialEq, Eq)]
25#[cfg_attr(feature = "defmt", derive(defmt::Format))]
26#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
27#[bitbybit::bitenum(u2, exhaustive = true)]
28pub enum AccessPerms {
29    /// Read-Write at EL1, No access at EL0
30    ReadWriteNoEL0 = 0b00,
31    /// Read-Write at EL1 and EL0
32    ReadWrite = 0b01,
33    /// Read-Only at EL1, No access at EL0
34    ReadOnlyNoEL0 = 0b10,
35    /// Read-Only at EL1 and EL0
36    ReadOnly = 0b11,
37}
38
39/// PRBAR (*Protection Region Base Address Register*)
40#[bitbybit::bitfield(u32, debug, defmt_fields(feature = "defmt"))]
41pub struct Prbar {
42    /// Address
43    #[bits(6..=31, rw)]
44    base: u26,
45    /// Shareability
46    #[bits(3..=4, rw)]
47    shareability: Shareability,
48    /// Access Permissions
49    #[bits(1..=2, rw)]
50    access_perms: AccessPerms,
51    /// Execute Never
52    #[bits(0..=0, rw)]
53    nx: bool,
54}
55
56impl SysReg for Prbar {
57    const CP: u32 = 15;
58    const CRN: u32 = 6;
59    const OP1: u32 = 0;
60    const CRM: u32 = 3;
61    const OP2: u32 = 0;
62}
63
64impl crate::register::SysRegRead for Prbar {}
65
66impl Prbar {
67    #[inline]
68    /// Reads PRBAR (*Protection Region Base Address Register*)
69    pub fn read() -> Prbar {
70        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
71    }
72}
73
74impl crate::register::SysRegWrite for Prbar {}
75
76impl Prbar {
77    #[inline]
78    /// Writes PRBAR (*Protection Region Base Address Register*)
79    pub fn write(value: Self) {
80        unsafe {
81            <Self as SysRegWrite>::write_raw(value.raw_value());
82        }
83    }
84}
aarch32_cpu/register/armv8r/prbar.rs

aarch32_cpu/register/armv8r/
prbar.rs
