aarch32_cpu/register/armv8r/
hvbar.rs

1//! Code for HVBAR (*Hyp Vector Base Address Register*)
2
3use crate::register::{SysReg, SysRegRead, SysRegWrite};
4
5/// HVBAR (*Hyp Vector Base Address Register*)
6///
7/// There is no `modify` method because this register holds a single 32-bit address.
8///
9/// This is only available in EL2.
10#[derive(Debug, Clone, Copy, PartialEq, Eq)]
11#[repr(transparent)]
12#[cfg_attr(feature = "defmt", derive(defmt::Format))]
13#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
14pub struct Hvbar(pub u32);
15
16impl SysReg for Hvbar {
17    const CP: u32 = 15;
18    const CRN: u32 = 12;
19    const OP1: u32 = 4;
20    const CRM: u32 = 0;
21    const OP2: u32 = 0;
22}
23
24impl SysRegRead for Hvbar {}
25
26impl SysRegWrite for Hvbar {}
27
28impl Hvbar {
29    /// Read HVBAR (*Hyp Vector Base Address Register*)
30    #[inline]
31    pub fn read() -> Hvbar {
32        // Safety: Reading this register has no side-effects and is atomic
33        unsafe { Self(<Self as SysRegRead>::read_raw()) }
34    }
35
36    /// Write HVBAR (*Hyp Vector Base Address Register*)
37    ///
38    /// # Safety
39    ///
40    /// You must supply a correctly-aligned address of a valid Arm AArch32
41    /// Vector Table.
42    #[inline]
43    pub unsafe fn write(value: Self) {
44        // Safety: Writing this register is atomic
45        unsafe {
46            <Self as SysRegWrite>::write_raw(value.0 as u32);
47        }
48    }
49}
aarch32_cpu/register/armv8r/hvbar.rs

aarch32_cpu/register/armv8r/
hvbar.rs
