aarch32_cpu/register/armv8r/
hsctlr.rs

1//! Code for managing HSCTLR (*Hyp System Control Register*)
2
3use crate::register::{SysReg, SysRegRead, SysRegWrite};
4
5/// HSCTLR (*Hyp System Control Register*)
6#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
7pub struct Hsctlr {
8    /// T32 Exception Enable. Controls whether exceptions to EL2 are taken to A32 or T32 state
9    #[bits(30..=30, rw)]
10    te: bool,
11    /// Exception Endianness. The value of the PSTATE.E bit on entry to Hyp mode
12    #[bits(25..=25, rw)]
13    ee: bool,
14    /// Fast Interrupts enable
15    #[bits(21..=21, rw)]
16    fi: bool,
17    /// Write permission implies XN (Execute-never)
18    #[bits(19..=19, rw)]
19    wxn: bool,
20    /// Background Region enable for EL2
21    #[bits(17..=17, rw)]
22    br: bool,
23    /// Instruction access Cacheability control, for accesses at EL2
24    #[bits(12..=12, rw)]
25    i: bool,
26    /// SETEND instruction disable. Disables SETEND instructions at EL2
27    #[bits(8..=8, rw)]
28    sed: bool,
29    /// IT Disable. Disables some uses of IT instructions at EL2
30    #[bits(7..=7, rw)]
31    itd: bool,
32    /// System instruction memory barrier enable
33    #[bits(5..=5, rw)]
34    cp15ben: bool,
35    /// Cacheability control, for data accesses at EL2
36    #[bits(2..=2, rw)]
37    c: bool,
38    /// Alignment check enable
39    #[bits(1..=1, rw)]
40    a: bool,
41    /// MPU enable for the EL2 MPU
42    #[bits(0..=0, rw)]
43    m: bool,
44}
45
46impl SysReg for Hsctlr {
47    const CP: u32 = 15;
48    const CRN: u32 = 1;
49    const OP1: u32 = 4;
50    const CRM: u32 = 0;
51    const OP2: u32 = 0;
52}
53
54impl crate::register::SysRegRead for Hsctlr {}
55
56impl Hsctlr {
57    #[inline]
58    /// Reads HSCTLR (*Hyp System Control Register*)
59    pub fn read() -> Hsctlr {
60        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
61    }
62}
63
64impl crate::register::SysRegWrite for Hsctlr {}
65
66impl Hsctlr {
67    #[inline]
68    /// Writes HSCTLR (*Hyp System Control Register*)
69    pub fn write(value: Self) {
70        unsafe {
71            <Self as SysRegWrite>::write_raw(value.raw_value());
72        }
73    }
74    /// Read-modify-write this register
75    #[inline]
76    pub fn modify<F>(f: F)
77    where
78        F: FnOnce(&mut Self),
79    {
80        let mut val = Self::read();
81        f(&mut val);
82        Self::write(val);
83    }
84}
aarch32_cpu/register/armv8r/hsctlr.rs

aarch32_cpu/register/armv8r/
hsctlr.rs
