aarch32_cpu/register/armv8r/
hmpuir.rs

1//! Code for managing HMPUIR (*Hyp MPU Type Register*)
2
3use crate::register::{SysReg, SysRegRead};
4
5/// HMPUIR (*Hyp MPU Type Register*)
6#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
7#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
8pub struct Hmpuir {
9    /// The number of EL2 MPU regions implemented
10    #[bits(0..=7, r)]
11    region: u8,
12}
13
14impl SysReg for Hmpuir {
15    const CP: u32 = 15;
16    const CRN: u32 = 0;
17    const OP1: u32 = 4;
18    const CRM: u32 = 0;
19    const OP2: u32 = 4;
20}
21
22impl crate::register::SysRegRead for Hmpuir {}
23
24impl Hmpuir {
25    #[inline]
26    /// Reads HMPUIR (*Hyp MPU Type Register*)
27    pub fn read() -> Hmpuir {
28        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
29    }
30}