aarch32_cpu/register/armv8r/
hactlr.rs

1//! Code for managing HACTRL (*Hyp Auxiliary Control Register*)
2
3use crate::register::{SysReg, SysRegRead, SysRegWrite};
4
5/// HACTRL (*Hyp Auxiliary Control Register*)
6#[bitbybit::bitfield(u32)]
7#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
8pub struct Hactlr {
9    /// Controls access to IMP_TESTR1 at EL0 and EL1
10    #[bits(15..=15, rw)]
11    testr1: bool,
12    /// Controls access to IMP_DCERR0, IMP_DCERR1, IMP_ICERR0, IMP_ICERR1,
13    /// IMP_TCMERR0, IMP_TCMERR1, IMP_FLASHERR0, and IMP_FLASHERR1 registers
14    #[bits(13..=13, rw)]
15    err: bool,
16    /// Controls access to IMP_INTMONR at EL1
17    #[bits(12..=12, rw)]
18    intmonr: bool,
19    /// Controls access to IMP_BUSTIMEOUTR at EL1
20    #[bits(10..=10, rw)]
21    bustimeoutr: bool,
22    /// Controls access to QOSR at EL1
23    #[bits(9..=9, rw)]
24    qosr: bool,
25    /// Controls access to IMP_PERIPHPREGIONR at EL1
26    #[bits(8..=8, rw)]
27    periphpregionr: bool,
28    /// Controls access to IMP_FLASHIFREGIONR at EL1
29    #[bits(7..=7, rw)]
30    flashifregionr: bool,
31    /// Controls access to CDBGDCI at EL1
32    #[bits(1..=1, rw)]
33    cdbgdci: bool,
34    /// IMP_CPUACTLR write access control
35    #[bits(0..=0, rw)]
36    cpuactlr: bool,
37}
38
39impl SysReg for Hactlr {
40    const CP: u32 = 15;
41    const CRN: u32 = 1;
42    const OP1: u32 = 4;
43    const CRM: u32 = 0;
44    const OP2: u32 = 1;
45}
46
47impl SysRegRead for Hactlr {}
48
49impl SysRegWrite for Hactlr {}
50
51impl Hactlr {
52    /// Read HACTRL (*Hyp Auxiliary Control Register*)
53    #[inline]
54    pub fn read() -> Hactlr {
55        // Safety: Reading this register has no side-effects and is atomic
56        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
57    }
58
59    /// Write HACTRL (*Hyp Auxiliary Control Register*)
60    #[inline]
61    pub fn write(value: Self) {
62        // Safety: Writing this register is atomic
63        unsafe {
64            <Self as SysRegWrite>::write_raw(value.raw_value());
65        }
66    }
67
68    /// Modify HACTRL (*Hyp Auxiliary Control Register*)
69    #[inline]
70    pub fn modify<F>(f: F)
71    where
72        F: FnOnce(&mut Self),
73    {
74        let mut value = Self::read();
75        f(&mut value);
76        Self::write(value);
77    }
78}
79
80impl core::fmt::Debug for Hactlr {
81    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
82        write!(f, "HACTLR {{ CPUACTLR={}, CDBGDCI={}, FLASHIFREGIONR={}, PERIPHPREGIONR={}, QOSR={}, BUSTIMEOUTR={}, INTMONR={}, ERR={}, TESTR1={} }}",
83            self.cpuactlr() as u8,
84            self.cdbgdci() as u8,
85            self.flashifregionr() as u8,
86            self.periphpregionr() as u8,
87            self.qosr() as u8,
88            self.bustimeoutr() as u8,
89            self.intmonr() as u8,
90            self.err() as u8,
91            self.testr1() as u8
92        )
93    }
94}
95
96#[cfg(feature = "defmt")]
97impl defmt::Format for Hactlr {
98    fn format(&self, f: defmt::Formatter) {
99        defmt::write!(f, "HACTLR {{ CPUACTLR={0=0..1}, CDBGDCI={0=1..2}, FLASHIFREGIONR={0=7..8}, PERIPHPREGIONR={0=8..9}, QOSR={0=9..10}, BUSTIMEOUTR={0=10..11}, INTMONR={0=12..13}, ERR={0=13..14}, TESTR1={0=15..16} }}", self.raw_value())
100    }
101}
aarch32_cpu/register/armv8r/hactlr.rs

aarch32_cpu/register/armv8r/
hactlr.rs
