aarch32_cpu/register/armv8r/
cntp_tval.rs

1//! Code for managing CNTP_TVAL (*Physical Counter-timer TimerValue Register*)
2
3use crate::register::{SysReg, SysRegRead, SysRegWrite};
4
5/// CNTP_TVAL (*Physical Counter-timer TimerValue Register*)
6#[derive(Debug, Copy, Clone)]
7#[cfg_attr(feature = "defmt", derive(defmt::Format))]
8#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
9pub struct CntpTval(pub u32);
10
11impl SysReg for CntpTval {
12    const CP: u32 = 15;
13    const CRN: u32 = 14;
14    const OP1: u32 = 0;
15    const CRM: u32 = 2;
16    const OP2: u32 = 0;
17}
18
19impl SysRegRead for CntpTval {}
20
21impl CntpTval {
22    #[inline]
23    /// Reads CNTP_TVAL (*Physical Counter-timer TimerValue Register*)
24    pub fn read() -> CntpTval {
25        unsafe { Self(<Self as SysRegRead>::read_raw()) }
26    }
27}
28
29impl SysRegWrite for CntpTval {}
30
31impl CntpTval {
32    #[inline]
33    /// Writes CNTP_TVAL (*Physical Counter-timer TimerValue Register*)
34    pub fn write(value: Self) {
35        unsafe {
36            <Self as SysRegWrite>::write_raw(value.0);
37        }
38    }
39}