aarch32_cpu/register/armv8r/
cntp_cval.rs

1//! Code for managing CNTP_CVAL (*Physical Counter-timer CompareValue Register*)
2
3use crate::register::{SysReg64, SysRegRead64, SysRegWrite64};
4
5/// CNTP_CVAL (*Physical Counter-timer CompareValue Register*)
6#[derive(Debug, Copy, Clone)]
7#[cfg_attr(feature = "defmt", derive(defmt::Format))]
8#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
9pub struct CntpCval(pub u64);
10
11impl SysReg64 for CntpCval {
12    const CP: u32 = 15;
13    const OP1: u32 = 2;
14    const CRM: u32 = 14;
15}
16
17impl SysRegRead64 for CntpCval {}
18
19impl CntpCval {
20    #[inline]
21    /// Reads CNTP_CVAL (*Physical Counter-timer CompareValue Register*)
22    pub fn read() -> CntpCval {
23        unsafe { Self(<Self as SysRegRead64>::read_raw()) }
24    }
25}
26
27impl SysRegWrite64 for CntpCval {}
28
29impl CntpCval {
30    #[inline]
31    /// Writes CNTP_CVAL (*Physical Counter-timer CompareValue Register*)
32    pub fn write(value: Self) {
33        unsafe {
34            <Self as SysRegWrite64>::write_raw(value.0);
35        }
36    }
37}