aarch32_cpu/register/armv8r/
cntp_ctl.rs

1//! Code for managing CNTP_CTL (*Physical Counter-timer Control Register*)
2
3use crate::register::{SysReg, SysRegRead, SysRegWrite};
4
5/// CNTP_CTL (*Physical Counter-timer Control Register*)
6#[bitbybit::bitfield(u32, defmt_bitfields(feature = "defmt"))]
7#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
8pub struct CntpCtl {
9    /// The status of the timer interrupt.
10    #[bits(2..=2, r)]
11    istatus: bool,
12    /// Timer interrupt mask bit.
13    ///
14    /// * true: masked
15    /// * false: not masked
16    #[bits(1..=1, rw)]
17    imask: bool,
18    /// Enables the timer.
19    #[bits(0..=0, rw)]
20    enable: bool,
21}
22
23impl core::fmt::Debug for CntpCtl {
24    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
25        f.debug_struct("CntpCtl")
26            .field("istatus", &self.istatus())
27            .field("imask", &self.imask())
28            .field("enable", &self.enable())
29            .finish()
30    }
31}
32
33impl SysReg for CntpCtl {
34    const CP: u32 = 15;
35    const CRN: u32 = 14;
36    const OP1: u32 = 0;
37    const CRM: u32 = 2;
38    const OP2: u32 = 1;
39}
40
41impl SysRegRead for CntpCtl {}
42
43impl CntpCtl {
44    #[inline]
45    /// Reads CNTP_CTL (*Physical Counter-timer Control Register*)
46    pub fn read() -> CntpCtl {
47        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
48    }
49}
50
51impl SysRegWrite for CntpCtl {}
52
53impl CntpCtl {
54    #[inline]
55    /// Writes CNTP_CTL (*Physical Counter-timer Control Register*)
56    pub fn write(value: Self) {
57        unsafe {
58            <Self as SysRegWrite>::write_raw(value.raw_value());
59        }
60    }
61
62    #[inline]
63    /// Modifies CNTP_CTL (*Physical Counter-timer Control Register*)
64    pub fn modify<F>(f: F)
65    where
66        F: FnOnce(&mut Self),
67    {
68        let mut value = Self::read();
69        f(&mut value);
70        Self::write(value);
71    }
72}
aarch32_cpu/register/armv8r/cntp_ctl.rs

aarch32_cpu/register/armv8r/
cntp_ctl.rs
