aarch32_cpu/register/armv8r/
cnthp_ctl.rs

1//! Code for managing CNTHP_CTL (*Hyp Physical Counter-timer Control Register (EL2)*)
2
3use crate::register::{SysReg, SysRegRead, SysRegWrite};
4
5/// CNTHP_CTL (*Hyp Physical Counter-timer Control Register (EL2)*)
6#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
7#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
8pub struct CnthpCtl {
9    /// The status of the timer interrupt.
10    #[bit(2, r)]
11    istatus: bool,
12    /// Timer interrupt mask bit.
13    ///
14    /// * true: masked
15    /// * false: not masked
16    #[bit(1, rw)]
17    imask: bool,
18    /// Enables the timer.
19    #[bit(0, rw)]
20    enable: bool,
21}
22
23impl SysReg for CnthpCtl {
24    const CP: u32 = 15;
25    const CRN: u32 = 14;
26    const OP1: u32 = 4;
27    const CRM: u32 = 2;
28    const OP2: u32 = 1;
29}
30
31impl SysRegRead for CnthpCtl {}
32
33impl CnthpCtl {
34    #[inline]
35    /// Reads CNTHP_CTL (*Hyp Physical Counter-timer Control Register (EL2)*)
36    pub fn read() -> CnthpCtl {
37        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
38    }
39}
40
41impl SysRegWrite for CnthpCtl {}
42
43impl CnthpCtl {
44    #[inline]
45    /// Writes CNTHP_CTL (*Hyp Physical Counter-timer Control Register (EL2)*)
46    pub fn write(value: Self) {
47        unsafe {
48            <Self as SysRegWrite>::write_raw(value.raw_value());
49        }
50    }
51
52    /// Modify CNTHP_CTL (*Hyp Physical Counter-timer Control Register (EL2)*)
53    #[inline]
54    pub fn modify<F>(f: F)
55    where
56        F: FnOnce(&mut Self),
57    {
58        let mut value = Self::read();
59        f(&mut value);
60        Self::write(value);
61    }
62}
aarch32_cpu/register/armv8r/cnthp_ctl.rs

aarch32_cpu/register/armv8r/
cnthp_ctl.rs
