aarch32_cpu/register/armv8r/
cnthctl.rs

1//! Code for managing CNTHCTL (*Hyp Counter-timer Control Register*)
2
3use arbitrary_int::u4;
4
5use crate::register::{SysReg, SysRegRead, SysRegWrite};
6
7/// CNTHCTL (*Hyp Counter-timer Control Register*)
8#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
9#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
10pub struct Cnthctl {
11    #[bits(19..=19, rw)]
12    cntpmask: bool,
13    #[bits(18..=18, rw)]
14    cntvmask: bool,
15    #[bits(17..=17, rw)]
16    evntis: bool,
17    #[bits(16..=16, rw)]
18    el1nvvct: bool,
19    #[bits(15..=15, rw)]
20    el1nvpct: bool,
21    #[bits(14..=14, rw)]
22    el1tvct: bool,
23    #[bits(13..=13, rw)]
24    el1tvt: bool,
25    #[bits(12..=12, rw)]
26    ecv: bool,
27    #[bits(11..=11, rw)]
28    el1pten: bool,
29    #[bits(10..=10, rw)]
30    el1pcten: bool,
31    #[bits(9..=9, rw)]
32    el0pten: bool,
33    #[bits(8..=8, rw)]
34    el0vten: bool,
35    #[bits(4..=7, rw)]
36    evnti: u4,
37    #[bits(3..=3, rw)]
38    evntdir: bool,
39    #[bits(2..=2, rw)]
40    evnten: bool,
41    #[bits(1..=1, rw)]
42    el0vcten: bool,
43    #[bits(0..=0, rw)]
44    el0pcten: bool,
45}
46
47impl SysReg for Cnthctl {
48    const CP: u32 = 15;
49    const CRN: u32 = 14;
50    const OP1: u32 = 4;
51    const CRM: u32 = 1;
52    const OP2: u32 = 0;
53}
54
55impl SysRegRead for Cnthctl {}
56
57impl Cnthctl {
58    #[inline]
59    /// Reads CNTHCTL (*Hyp Counter-timer Control Register*)
60    pub fn read() -> Cnthctl {
61        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
62    }
63}
64
65impl SysRegWrite for Cnthctl {}
66
67impl Cnthctl {
68    #[inline]
69    /// Writes CNTHCTL (*Hyp Counter-timer Control Register*)
70    pub fn write(value: Self) {
71        unsafe {
72            <Self as SysRegWrite>::write_raw(value.raw_value());
73        }
74    }
75}
aarch32_cpu/register/armv8r/cnthctl.rs

aarch32_cpu/register/armv8r/
cnthctl.rs
