PY32m030xx_pac/tim3/
dcr.rs

1#[doc = "Register `DCR` reader"]
2pub struct R(crate::R<DCR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DCR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DCR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DCR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `DCR` writer"]
17pub struct W(crate::W<DCR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DCR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DCR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DCR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `DBA` reader - DMA base address"]
38pub type DBA_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `DBA` writer - DMA base address"]
40pub type DBA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCR_SPEC, u8, u8, 5, O>;
41#[doc = "Field `DBL` reader - DMA burst length"]
42pub type DBL_R = crate::FieldReader<u8, u8>;
43#[doc = "Field `DBL` writer - DMA burst length"]
44pub type DBL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCR_SPEC, u8, u8, 5, O>;
45impl R {
46    #[doc = "Bits 0:4 - DMA base address"]
47    #[inline(always)]
48    pub fn dba(&self) -> DBA_R {
49        DBA_R::new((self.bits & 0x1f) as u8)
50    }
51    #[doc = "Bits 8:12 - DMA burst length"]
52    #[inline(always)]
53    pub fn dbl(&self) -> DBL_R {
54        DBL_R::new(((self.bits >> 8) & 0x1f) as u8)
55    }
56}
57impl W {
58    #[doc = "Bits 0:4 - DMA base address"]
59    #[inline(always)]
60    pub fn dba(&mut self) -> DBA_W<0> {
61        DBA_W::new(self)
62    }
63    #[doc = "Bits 8:12 - DMA burst length"]
64    #[inline(always)]
65    pub fn dbl(&mut self) -> DBL_W<8> {
66        DBL_W::new(self)
67    }
68    #[doc = "Writes raw bits to the register."]
69    #[inline(always)]
70    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
71        self.0.bits(bits);
72        self
73    }
74}
75#[doc = "DMA control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcr](index.html) module"]
76pub struct DCR_SPEC;
77impl crate::RegisterSpec for DCR_SPEC {
78    type Ux = u32;
79}
80#[doc = "`read()` method returns [dcr::R](R) reader structure"]
81impl crate::Readable for DCR_SPEC {
82    type Reader = R;
83}
84#[doc = "`write(|w| ..)` method takes [dcr::W](W) writer structure"]
85impl crate::Writable for DCR_SPEC {
86    type Writer = W;
87}
88#[doc = "`reset()` method sets DCR to value 0"]
89impl crate::Resettable for DCR_SPEC {
90    #[inline(always)]
91    fn reset_value() -> Self::Ux {
92        0
93    }
94}
PY32m030xx_pac/tim3/dcr.rs

PY32m030xx_pac/tim3/
dcr.rs
