PY32T020xx_pac/rcc/
bdcr.rs

1#[doc = "Register `BDCR` reader"]
2pub struct R(crate::R<BDCR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<BDCR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<BDCR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<BDCR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `BDCR` writer"]
17pub struct W(crate::W<BDCR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<BDCR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<BDCR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<BDCR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `LSEON` reader - LSE oscillator enable"]
38pub type LSEON_R = crate::BitReader<bool>;
39#[doc = "Field `LSEON` writer - LSE oscillator enable"]
40pub type LSEON_W<'a, const O: u8> = crate::BitWriter<'a, u32, BDCR_SPEC, bool, O>;
41#[doc = "Field `LSERDY` reader - LSE oscillator ready"]
42pub type LSERDY_R = crate::BitReader<bool>;
43#[doc = "Field `LSERDY` writer - LSE oscillator ready"]
44pub type LSERDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, BDCR_SPEC, bool, O>;
45#[doc = "Field `LSEBYP` reader - LSE oscillator bypass"]
46pub type LSEBYP_R = crate::BitReader<bool>;
47#[doc = "Field `LSEBYP` writer - LSE oscillator bypass"]
48pub type LSEBYP_W<'a, const O: u8> = crate::BitWriter<'a, u32, BDCR_SPEC, bool, O>;
49#[doc = "Field `LSECSSON` reader - LSE CSS enable"]
50pub type LSECSSON_R = crate::BitReader<bool>;
51#[doc = "Field `LSECSSON` writer - LSE CSS enable"]
52pub type LSECSSON_W<'a, const O: u8> = crate::BitWriter<'a, u32, BDCR_SPEC, bool, O>;
53#[doc = "Field `LSECSSD` reader - LSE CSS detect"]
54pub type LSECSSD_R = crate::BitReader<bool>;
55#[doc = "Field `LSECSSD` writer - LSE CSS detect"]
56pub type LSECSSD_W<'a, const O: u8> = crate::BitWriter<'a, u32, BDCR_SPEC, bool, O>;
57#[doc = "Field `RTCSEL` reader - RTC clock source selection"]
58pub type RTCSEL_R = crate::FieldReader<u8, u8>;
59#[doc = "Field `RTCSEL` writer - RTC clock source selection"]
60pub type RTCSEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BDCR_SPEC, u8, u8, 2, O>;
61#[doc = "Field `RTC_HSEDIV_SEL` reader - "]
62pub type RTC_HSEDIV_SEL_R = crate::FieldReader<u8, u8>;
63#[doc = "Field `RTC_HSEDIV_SEL` writer - "]
64pub type RTC_HSEDIV_SEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BDCR_SPEC, u8, u8, 2, O>;
65#[doc = "Field `RTCEN` reader - RTC clock source enable"]
66pub type RTCEN_R = crate::BitReader<bool>;
67#[doc = "Field `RTCEN` writer - RTC clock source enable"]
68pub type RTCEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, BDCR_SPEC, bool, O>;
69#[doc = "Field `BDRST` reader - RTC domain software reset"]
70pub type BDRST_R = crate::BitReader<bool>;
71#[doc = "Field `BDRST` writer - RTC domain software reset"]
72pub type BDRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, BDCR_SPEC, bool, O>;
73#[doc = "Field `LSCSEL` reader - "]
74pub type LSCSEL_R = crate::BitReader<bool>;
75#[doc = "Field `LSCSEL` writer - "]
76pub type LSCSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, BDCR_SPEC, bool, O>;
77impl R {
78    #[doc = "Bit 0 - LSE oscillator enable"]
79    #[inline(always)]
80    pub fn lseon(&self) -> LSEON_R {
81        LSEON_R::new((self.bits & 1) != 0)
82    }
83    #[doc = "Bit 1 - LSE oscillator ready"]
84    #[inline(always)]
85    pub fn lserdy(&self) -> LSERDY_R {
86        LSERDY_R::new(((self.bits >> 1) & 1) != 0)
87    }
88    #[doc = "Bit 2 - LSE oscillator bypass"]
89    #[inline(always)]
90    pub fn lsebyp(&self) -> LSEBYP_R {
91        LSEBYP_R::new(((self.bits >> 2) & 1) != 0)
92    }
93    #[doc = "Bit 5 - LSE CSS enable"]
94    #[inline(always)]
95    pub fn lsecsson(&self) -> LSECSSON_R {
96        LSECSSON_R::new(((self.bits >> 5) & 1) != 0)
97    }
98    #[doc = "Bit 6 - LSE CSS detect"]
99    #[inline(always)]
100    pub fn lsecssd(&self) -> LSECSSD_R {
101        LSECSSD_R::new(((self.bits >> 6) & 1) != 0)
102    }
103    #[doc = "Bits 8:9 - RTC clock source selection"]
104    #[inline(always)]
105    pub fn rtcsel(&self) -> RTCSEL_R {
106        RTCSEL_R::new(((self.bits >> 8) & 3) as u8)
107    }
108    #[doc = "Bits 10:11"]
109    #[inline(always)]
110    pub fn rtc_hsediv_sel(&self) -> RTC_HSEDIV_SEL_R {
111        RTC_HSEDIV_SEL_R::new(((self.bits >> 10) & 3) as u8)
112    }
113    #[doc = "Bit 15 - RTC clock source enable"]
114    #[inline(always)]
115    pub fn rtcen(&self) -> RTCEN_R {
116        RTCEN_R::new(((self.bits >> 15) & 1) != 0)
117    }
118    #[doc = "Bit 16 - RTC domain software reset"]
119    #[inline(always)]
120    pub fn bdrst(&self) -> BDRST_R {
121        BDRST_R::new(((self.bits >> 16) & 1) != 0)
122    }
123    #[doc = "Bit 25"]
124    #[inline(always)]
125    pub fn lscsel(&self) -> LSCSEL_R {
126        LSCSEL_R::new(((self.bits >> 25) & 1) != 0)
127    }
128}
129impl W {
130    #[doc = "Bit 0 - LSE oscillator enable"]
131    #[inline(always)]
132    pub fn lseon(&mut self) -> LSEON_W<0> {
133        LSEON_W::new(self)
134    }
135    #[doc = "Bit 1 - LSE oscillator ready"]
136    #[inline(always)]
137    pub fn lserdy(&mut self) -> LSERDY_W<1> {
138        LSERDY_W::new(self)
139    }
140    #[doc = "Bit 2 - LSE oscillator bypass"]
141    #[inline(always)]
142    pub fn lsebyp(&mut self) -> LSEBYP_W<2> {
143        LSEBYP_W::new(self)
144    }
145    #[doc = "Bit 5 - LSE CSS enable"]
146    #[inline(always)]
147    pub fn lsecsson(&mut self) -> LSECSSON_W<5> {
148        LSECSSON_W::new(self)
149    }
150    #[doc = "Bit 6 - LSE CSS detect"]
151    #[inline(always)]
152    pub fn lsecssd(&mut self) -> LSECSSD_W<6> {
153        LSECSSD_W::new(self)
154    }
155    #[doc = "Bits 8:9 - RTC clock source selection"]
156    #[inline(always)]
157    pub fn rtcsel(&mut self) -> RTCSEL_W<8> {
158        RTCSEL_W::new(self)
159    }
160    #[doc = "Bits 10:11"]
161    #[inline(always)]
162    pub fn rtc_hsediv_sel(&mut self) -> RTC_HSEDIV_SEL_W<10> {
163        RTC_HSEDIV_SEL_W::new(self)
164    }
165    #[doc = "Bit 15 - RTC clock source enable"]
166    #[inline(always)]
167    pub fn rtcen(&mut self) -> RTCEN_W<15> {
168        RTCEN_W::new(self)
169    }
170    #[doc = "Bit 16 - RTC domain software reset"]
171    #[inline(always)]
172    pub fn bdrst(&mut self) -> BDRST_W<16> {
173        BDRST_W::new(self)
174    }
175    #[doc = "Bit 25"]
176    #[inline(always)]
177    pub fn lscsel(&mut self) -> LSCSEL_W<25> {
178        LSCSEL_W::new(self)
179    }
180    #[doc = "Writes raw bits to the register."]
181    #[inline(always)]
182    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
183        self.0.bits(bits);
184        self
185    }
186}
187#[doc = "RTC domain control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bdcr](index.html) module"]
188pub struct BDCR_SPEC;
189impl crate::RegisterSpec for BDCR_SPEC {
190    type Ux = u32;
191}
192#[doc = "`read()` method returns [bdcr::R](R) reader structure"]
193impl crate::Readable for BDCR_SPEC {
194    type Reader = R;
195}
196#[doc = "`write(|w| ..)` method takes [bdcr::W](W) writer structure"]
197impl crate::Writable for BDCR_SPEC {
198    type Writer = W;
199}
200#[doc = "`reset()` method sets BDCR to value 0"]
201impl crate::Resettable for BDCR_SPEC {
202    #[inline(always)]
203    fn reset_value() -> Self::Ux {
204        0
205    }
206}
PY32T020xx_pac/rcc/bdcr.rs

PY32T020xx_pac/rcc/
bdcr.rs
