[−][src]Struct ADuCM302x::generic::W
Implementations
impl<U, REG> W<U, REG>[src]
impl W<u16, Reg<u16, _LOAD>>[src]
impl W<u16, Reg<u16, _CTL>>[src]
pub fn pre(&mut self) -> PRE_W<'_>[src]
Bits 0:1 - Prescaler
pub fn up(&mut self) -> UP_W<'_>[src]
Bit 2 - Count up
pub fn mode(&mut self) -> MODE_W<'_>[src]
Bit 3 - Timer Mode
pub fn en(&mut self) -> EN_W<'_>[src]
Bit 4 - Timer Enable
pub fn clk(&mut self) -> CLK_W<'_>[src]
Bits 5:6 - Clock Select
pub fn rld(&mut self) -> RLD_W<'_>[src]
Bit 7 - Reload Control
pub fn evtrange(&mut self) -> EVTRANGE_W<'_>[src]
Bits 8:12 - Event Select Range
pub fn evten(&mut self) -> EVTEN_W<'_>[src]
Bit 13 - Event Select
pub fn rsten(&mut self) -> RSTEN_W<'_>[src]
Bit 14 - Counter and Prescale Reset Enable
pub fn syncbyp(&mut self) -> SYNCBYP_W<'_>[src]
Bit 15 - Synchronization Bypass
impl W<u16, Reg<u16, _CLRINT>>[src]
pub fn timeout(&mut self) -> TIMEOUT_W<'_>[src]
Bit 0 - Clear Timeout Interrupt
pub fn evtcapt(&mut self) -> EVTCAPT_W<'_>[src]
Bit 1 - Clear Captured Event Interrupt
impl W<u16, Reg<u16, _ALOAD>>[src]
impl W<u16, Reg<u16, _PWMCTL>>[src]
pub fn match_(&mut self) -> MATCH_W<'_>[src]
Bit 0 - PWM Match Enabled
pub fn idlestate(&mut self) -> IDLESTATE_W<'_>[src]
Bit 1 - PWM Idle State
impl W<u16, Reg<u16, _PWMMATCH>>[src]
impl W<u16, Reg<u16, _CR0>>[src]
pub fn cnten(&mut self) -> CNTEN_W<'_>[src]
Bit 0 - Global Enable for the RTC
pub fn almen(&mut self) -> ALMEN_W<'_>[src]
Bit 1 - Enable the RTC Alarm (Absolute) Operation
pub fn alminten(&mut self) -> ALMINTEN_W<'_>[src]
Bit 2 - Enable ALMINT Sourced Alarm Interrupts to the CPU
pub fn trmen(&mut self) -> TRMEN_W<'_>[src]
Bit 3 - Enable RTC Digital Trimming
pub fn mod60almen(&mut self) -> MOD60ALMEN_W<'_>[src]
Bit 4 - Enable RTC Modulo-60 Counting of Time Past a Modulo-60 Boundary
pub fn mod60alm(&mut self) -> MOD60ALM_W<'_>[src]
Bits 5:10 - Periodic, Modulo-60 Alarm Time in Prescaled RTC Time Units Beyond a Modulo-60 Boundary
pub fn mod60alminten(&mut self) -> MOD60ALMINTEN_W<'_>[src]
Bit 11 - Enable Periodic Modulo-60 RTC Alarm Sourced Interrupts to the CPU
pub fn isointen(&mut self) -> ISOINTEN_W<'_>[src]
Bit 12 - Enable ISOINT Sourced Interrupts to the CPU When Isolation of the RTC Power Domain is Activated and Subsequently De-activated
pub fn wpnderrinten(&mut self) -> WPNDERRINTEN_W<'_>[src]
Bit 13 - Enable Write Pending Error Sourced Interrupts to the CPU When an RTC Register-write Pending Error Occurs
pub fn wsyncinten(&mut self) -> WSYNCINTEN_W<'_>[src]
Bit 14 - Enable Write Synchronization Sourced Interrupts to the CPU
pub fn wpndinten(&mut self) -> WPNDINTEN_W<'_>[src]
Bit 15 - Enable Write Pending Sourced Interrupts to the CPU
impl W<u16, Reg<u16, _SR0>>[src]
pub fn almint(&mut self) -> ALMINT_W<'_>[src]
Bit 1 - Alarm Interrupt Source
pub fn mod60almint(&mut self) -> MOD60ALMINT_W<'_>[src]
Bit 2 - Modulo-60 RTC Alarm Interrupt Source
pub fn isoint(&mut self) -> ISOINT_W<'_>[src]
Bit 3 - RTC Power-Domain Isolation Interrupt Source
pub fn wpnderrint(&mut self) -> WPNDERRINT_W<'_>[src]
Bit 4 - Write Pending Error Interrupt Source
pub fn wsyncint(&mut self) -> WSYNCINT_W<'_>[src]
Bit 5 - Write Synchronisation Interrupt
pub fn wpndint(&mut self) -> WPNDINT_W<'_>[src]
Bit 6 - Write Pending Interrupt
impl W<u16, Reg<u16, _CNT0>>[src]
pub fn value(&mut self) -> VALUE_W<'_>[src]
Bits 0:15 - Lower 16 Prescaled (Non-Fractional) Bits of the RTC Real-Time Count
impl W<u16, Reg<u16, _CNT1>>[src]
pub fn value(&mut self) -> VALUE_W<'_>[src]
Bits 0:15 - Upper 16 Prescaled (Non-Fractional) Bits of the RTC Real-Time Count
impl W<u16, Reg<u16, _ALM0>>[src]
pub fn value(&mut self) -> VALUE_W<'_>[src]
Bits 0:15 - Lower 16 Prescaled (i.e. Non-Fractional) Bits of the RTC Alarm Target Time
impl W<u16, Reg<u16, _ALM1>>[src]
pub fn value(&mut self) -> VALUE_W<'_>[src]
Bits 0:15 - Upper 16 Prescaled (Non-Fractional) Bits of the RTC Alarm Target Time
impl W<u16, Reg<u16, _TRM>>[src]
pub fn value(&mut self) -> VALUE_W<'_>[src]
Bits 0:2 - Trim Value in Prescaled RTC Time Units to Be Added or Subtracted from the RTC Count at the End of a Periodic Interval Selected by TRM:TRMIVL
pub fn add(&mut self) -> ADD_W<'_>[src]
Bit 3 - Trim Polarity
pub fn ivl(&mut self) -> IVL_W<'_>[src]
Bits 4:5 - Trim Interval in Prescaled RTC Time Units
pub fn ivl2expmin(&mut self) -> IVL2EXPMIN_W<'_>[src]
Bits 6:9 - Minimum Power-of-two Interval of Prescaled RTC Time Units Which TRM:TRMIVL TRMIVL Can Select
impl W<u16, Reg<u16, _GWY>>[src]
impl W<u16, Reg<u16, _CR1>>[src]
pub fn cntinten(&mut self) -> CNTINTEN_W<'_>[src]
Bit 0 - Enable for the RTC Count Interrupt Source
pub fn psinten(&mut self) -> PSINTEN_W<'_>[src]
Bit 1 - Enable for the Prescaled, Modulo-1 Interrupt Source, in SR2:RTCPSINT
pub fn trminten(&mut self) -> TRMINTEN_W<'_>[src]
Bit 2 - Enable for the RTC Trim Interrupt Source, in SR2:RTCTRMINT
pub fn cntrollinten(&mut self) -> CNTROLLINTEN_W<'_>[src]
Bit 3 - Enable for the RTC Count Roll-Over Interrupt Source, in SR2:RTCCNTROLLINT
pub fn cntmod60rollinten(&mut self) -> CNTMOD60ROLLINTEN_W<'_>[src]
Bit 4 - Enable for the RTC Modulo-60 Count Roll-Over Interrupt Source, in SR2:RTCCNTMOD60ROLLINT
pub fn prescale2exp(&mut self) -> PRESCALE2EXP_W<'_>[src]
Bits 5:8 - Prescale Power of 2 Division Factor for the RTC Base Clock
impl W<u16, Reg<u16, _SR2>>[src]
pub fn cntint(&mut self) -> CNTINT_W<'_>[src]
Bit 0 - RTC Count Interrupt Source
pub fn psint(&mut self) -> PSINT_W<'_>[src]
Bit 1 - RTC Prescaled, Modulo-1 Boundary Interrupt Source
pub fn trmint(&mut self) -> TRMINT_W<'_>[src]
Bit 2 - RTC Trim Interrupt Source
pub fn cntrollint(&mut self) -> CNTROLLINT_W<'_>[src]
Bit 3 - RTC Count Roll-Over Interrupt Source
pub fn cntmod60rollint(&mut self) -> CNTMOD60ROLLINT_W<'_>[src]
Bit 4 - RTC Modulo-60 Count Roll-Over Interrupt Source
impl W<u16, Reg<u16, _ALM2>>[src]
impl W<u16, Reg<u16, _SR3>>[src]
pub fn ic0irq(&mut self) -> IC0IRQ_W<'_>[src]
Bit 0 - Sticky Interrupt Source for the RTC Input Capture Channel 0
pub fn ic2irq(&mut self) -> IC2IRQ_W<'_>[src]
Bit 2 - Sticky Interrupt Source for the RTC Input Capture Channel 2
pub fn ic3irq(&mut self) -> IC3IRQ_W<'_>[src]
Bit 3 - Sticky Interrupt Source for the RTC Input Capture Channel 3
pub fn ic4irq(&mut self) -> IC4IRQ_W<'_>[src]
Bit 4 - Sticky Interrupt Source for the RTC Input Capture Channel 4
pub fn ss1irq(&mut self) -> SS1IRQ_W<'_>[src]
Bit 9 - Sticky Interrupt Source for SensorStrobe Channel 1
impl W<u16, Reg<u16, _CR2IC>>[src]
pub fn ic0en(&mut self) -> IC0EN_W<'_>[src]
Bit 0 - Enable for the RTC Input Capture Channel 0
pub fn ic2en(&mut self) -> IC2EN_W<'_>[src]
Bit 2 - Enable for the RTC Input Capture Channel 2
pub fn ic3en(&mut self) -> IC3EN_W<'_>[src]
Bit 3 - Enable for the RTC Input Capture Channel 3
pub fn ic4en(&mut self) -> IC4EN_W<'_>[src]
Bit 4 - Enable for the RTC Input Capture Channel 4
pub fn ic0lh(&mut self) -> IC0LH_W<'_>[src]
Bit 5 - Polarity of the Active-Going Capture Edge for the RTC Input Capture Channel 0
pub fn ic2lh(&mut self) -> IC2LH_W<'_>[src]
Bit 7 - Polarity of the Active-going Capture Edge for the Input Capture Channel 2
pub fn ic3lh(&mut self) -> IC3LH_W<'_>[src]
Bit 8 - Polarity of the Active-going Capture Edge for the Input Capture Channel 3
pub fn ic4lh(&mut self) -> IC4LH_W<'_>[src]
Bit 9 - Polarity of the Active-going Capture Edge for the Input Capture Channel 4
pub fn ic0irqen(&mut self) -> IC0IRQEN_W<'_>[src]
Bit 10 - Interrupt Enable for the RTC Input Capture Channel 0
pub fn ic2irqen(&mut self) -> IC2IRQEN_W<'_>[src]
Bit 12 - Interrupt Enable for the RTC Input Capture Channel 2
pub fn ic3irqen(&mut self) -> IC3IRQEN_W<'_>[src]
Bit 13 - Interrupt Enable for the RTC Input Capture Channel 3
pub fn ic4irqen(&mut self) -> IC4IRQEN_W<'_>[src]
Bit 14 - Interrupt Enable for the RTC Input Capture Channel 4
pub fn icowusen(&mut self) -> ICOWUSEN_W<'_>[src]
Bit 15 - Enable Overwrite of Unread Snapshots for All Input Capture Channels
impl W<u16, Reg<u16, _CR3SS>>[src]
pub fn ss1en(&mut self) -> SS1EN_W<'_>[src]
Bit 1 - Enable for SensorStrobe Channel 1
pub fn ss1irqen(&mut self) -> SS1IRQEN_W<'_>[src]
Bit 9 - Interrupt Enable for SensorStrobe Channel 1
impl W<u16, Reg<u16, _CR4SS>>[src]
pub fn ss1msken(&mut self) -> SS1MSKEN_W<'_>[src]
Bit 1 - Enable for Thermometer-Code Masking of the SensorStrobe Channel 1
pub fn ss1arlen(&mut self) -> SS1ARLEN_W<'_>[src]
Bit 9 - Enable for Auto-Reloading When SensorStrobe Match Occurs
impl W<u16, Reg<u16, _SSMSK>>[src]
pub fn ssmsk(&mut self) -> SSMSK_W<'_>[src]
Bits 0:15 - Thermometer-Encoded Masks for SensorStrobe Channels
impl W<u16, Reg<u16, _SS1ARL>>[src]
pub fn ss1arl(&mut self) -> SS1ARL_W<'_>[src]
Bits 0:15 - Auto-Reload Value When SensorStrobe Match Occurs
impl W<u16, Reg<u16, _SS1>>[src]
impl W<u16, Reg<u16, _SWDEN>>[src]
impl W<u16, Reg<u16, _LOAD>>[src]
impl W<u16, Reg<u16, _CTL>>[src]
pub fn irq(&mut self) -> IRQ_W<'_>[src]
Bit 1 - Timer Interrupt
pub fn pre(&mut self) -> PRE_W<'_>[src]
Bits 2:3 - Prescaler
pub fn en(&mut self) -> EN_W<'_>[src]
Bit 5 - Timer Enable
pub fn mode(&mut self) -> MODE_W<'_>[src]
Bit 6 - Timer Mode
pub fn spare(&mut self) -> SPARE_W<'_>[src]
Bit 7 - Unused Spare Bit
impl W<u16, Reg<u16, _RESTART>>[src]
impl W<u16, Reg<u16, _MCTL>>[src]
pub fn masen(&mut self) -> MASEN_W<'_>[src]
Bit 0 - Master Enable
pub fn complete(&mut self) -> COMPLETE_W<'_>[src]
Bit 1 - Start Back-off Disable
pub fn loopback(&mut self) -> LOOPBACK_W<'_>[src]
Bit 2 - Internal Loopback Enable
pub fn stretchscl(&mut self) -> STRETCHSCL_W<'_>[src]
Bit 3 - Stretch SCL Enable
pub fn ienmrx(&mut self) -> IENMRX_W<'_>[src]
Bit 4 - Receive Request Interrupt Enable
pub fn ienmtx(&mut self) -> IENMTX_W<'_>[src]
Bit 5 - Transmit Request Interrupt Enable
pub fn ienalost(&mut self) -> IENALOST_W<'_>[src]
Bit 6 - Arbitration Lost Interrupt Enable
pub fn ienack(&mut self) -> IENACK_W<'_>[src]
Bit 7 - ACK Not Received Interrupt Enable
pub fn iencmp(&mut self) -> IENCMP_W<'_>[src]
Bit 8 - Transaction Completed (or Stop Detected) Interrupt Enable
pub fn mxmitdec(&mut self) -> MXMITDEC_W<'_>[src]
Bit 9 - Decrement Master Tx FIFO Status When a Byte Txed
pub fn mrxdma(&mut self) -> MRXDMA_W<'_>[src]
Bit 10 - Enable Master Rx DMA Request
pub fn mtxdma(&mut self) -> MTXDMA_W<'_>[src]
Bit 11 - Enable Master Tx DMA Request
pub fn busclr(&mut self) -> BUSCLR_W<'_>[src]
Bit 12 - Bus-Clear Enable
pub fn stopbusclr(&mut self) -> STOPBUSCLR_W<'_>[src]
Bit 13 - Prestop Bus Clear
impl W<u16, Reg<u16, _MSTAT>>[src]
pub fn mtxreq(&mut self) -> MTXREQ_W<'_>[src]
Bit 2 - Master Transmit Request/Clear Master Transmit Interrupt
impl W<u16, Reg<u16, _MTX>>[src]
impl W<u16, Reg<u16, _MRXCNT>>[src]
pub fn value(&mut self) -> VALUE_W<'_>[src]
Bits 0:7 - Receive Count
pub fn extend(&mut self) -> EXTEND_W<'_>[src]
Bit 8 - Extended Read
impl W<u16, Reg<u16, _ADDR1>>[src]
impl W<u16, Reg<u16, _ADDR2>>[src]
impl W<u16, Reg<u16, _BYT>>[src]
impl W<u16, Reg<u16, _DIV>>[src]
pub fn low(&mut self) -> LOW_W<'_>[src]
Bits 0:7 - Serial Clock Low Time
pub fn high(&mut self) -> HIGH_W<'_>[src]
Bits 8:15 - Serial Clock High Time
impl W<u16, Reg<u16, _SCTL>>[src]
pub fn slven(&mut self) -> SLVEN_W<'_>[src]
Bit 0 - Slave Enable
pub fn adr10en(&mut self) -> ADR10EN_W<'_>[src]
Bit 1 - Enabled 10-bit Addressing
pub fn gcen(&mut self) -> GCEN_W<'_>[src]
Bit 2 - General Call Enable
pub fn hgcen(&mut self) -> HGCEN_W<'_>[src]
Bit 3 - Hardware General Call Enable
pub fn gcsbclr(&mut self) -> GCSBCLR_W<'_>[src]
Bit 4 - General Call Status Bit Clear
pub fn earlytxr(&mut self) -> EARLYTXR_W<'_>[src]
Bit 5 - Early Transmit Request Mode
pub fn nack(&mut self) -> NACK_W<'_>[src]
Bit 7 - NACK Next Communication
pub fn ienstop(&mut self) -> IENSTOP_W<'_>[src]
Bit 8 - Stop Condition Detected Interrupt Enable
pub fn iensrx(&mut self) -> IENSRX_W<'_>[src]
Bit 9 - Slave Receive Request Interrupt Enable
pub fn ienstx(&mut self) -> IENSTX_W<'_>[src]
Bit 10 - Slave Transmit Request Interrupt Enable
pub fn stxdec(&mut self) -> STXDEC_W<'_>[src]
Bit 11 - Decrement Slave Tx FIFO Status When a Byte is Txed
pub fn ienrepst(&mut self) -> IENREPST_W<'_>[src]
Bit 12 - Repeated Start Interrupt Enable
pub fn srxdma(&mut self) -> SRXDMA_W<'_>[src]
Bit 13 - Enable Slave Rx DMA Request
pub fn stxdma(&mut self) -> STXDMA_W<'_>[src]
Bit 14 - Enable Slave Tx DMA Request
impl W<u16, Reg<u16, _SSTAT>>[src]
pub fn stxfsereq(&mut self) -> STXFSEREQ_W<'_>[src]
Bit 0 - Slave Tx FIFO Status or Early Request
impl W<u16, Reg<u16, _STX>>[src]
impl W<u16, Reg<u16, _ALT>>[src]
impl W<u16, Reg<u16, _ID0>>[src]
impl W<u16, Reg<u16, _ID1>>[src]
impl W<u16, Reg<u16, _ID2>>[src]
impl W<u16, Reg<u16, _ID3>>[src]
impl W<u16, Reg<u16, _STAT>>[src]
pub fn sflush(&mut self) -> SFLUSH_W<'_>[src]
Bit 8 - Flush the Slave Transmit FIFO
pub fn mflush(&mut self) -> MFLUSH_W<'_>[src]
Bit 9 - Flush the Master Transmit FIFO
impl W<u16, Reg<u16, _SHCTL>>[src]
impl W<u16, Reg<u16, _TCTL>>[src]
pub fn thdatin(&mut self) -> THDATIN_W<'_>[src]
Bits 0:4 - Data in Hold Start
pub fn filteroff(&mut self) -> FILTEROFF_W<'_>[src]
Bit 8 - Input Filter Control
impl W<u16, Reg<u16, _ASTRETCH_SCL>>[src]
pub fn mst(&mut self) -> MST_W<'_>[src]
Bits 0:3 - Master Automatic Stretch Mode
pub fn slv(&mut self) -> SLV_W<'_>[src]
Bits 4:7 - Slave Automatic Stretch Mode
impl W<u16, Reg<u16, _TX>>[src]
pub fn byte1(&mut self) -> BYTE1_W<'_>[src]
Bits 0:7 - 8-bit Transmit Buffer
pub fn byte2(&mut self) -> BYTE2_W<'_>[src]
Bits 8:15 - 8-bit Transmit Buffer, Used Only in DMA Modes
impl W<u16, Reg<u16, _DIV>>[src]
impl W<u16, Reg<u16, _CTL>>[src]
pub fn spien(&mut self) -> SPIEN_W<'_>[src]
Bit 0 - SPI Enable
pub fn masen(&mut self) -> MASEN_W<'_>[src]
Bit 1 - Master Mode Enable
pub fn cpha(&mut self) -> CPHA_W<'_>[src]
Bit 2 - Serial Clock Phase Mode
pub fn cpol(&mut self) -> CPOL_W<'_>[src]
Bit 3 - Serial Clock Polarity
pub fn wom(&mut self) -> WOM_W<'_>[src]
Bit 4 - SPI Wired-OR Mode
pub fn lsb(&mut self) -> LSB_W<'_>[src]
Bit 5 - LSB First Transfer Enable
pub fn tim(&mut self) -> TIM_W<'_>[src]
Bit 6 - SPI Transfer and Interrupt Mode
pub fn zen(&mut self) -> ZEN_W<'_>[src]
Bit 7 - Transmit Zeros Enable
pub fn rxof(&mut self) -> RXOF_W<'_>[src]
Bit 8 - Rx Overflow Overwrite Enable
pub fn oen(&mut self) -> OEN_W<'_>[src]
Bit 9 - Slave MISO Output Enable
pub fn loopback(&mut self) -> LOOPBACK_W<'_>[src]
Bit 10 - Loopback Enable
pub fn con(&mut self) -> CON_W<'_>[src]
Bit 11 - Continuous Transfer Enable
pub fn rflush(&mut self) -> RFLUSH_W<'_>[src]
Bit 12 - SPI Rx FIFO Flush Enable
pub fn tflush(&mut self) -> TFLUSH_W<'_>[src]
Bit 13 - SPI Tx FIFO Flush Enable
pub fn csrst(&mut self) -> CSRST_W<'_>[src]
Bit 14 - Reset Mode for CS Error Bit
impl W<u16, Reg<u16, _IEN>>[src]
pub fn irqmode(&mut self) -> IRQMODE_W<'_>[src]
Bits 0:2 - SPI IRQ Mode Bits
pub fn cs(&mut self) -> CS_W<'_>[src]
Bit 8 - Enable Interrupt on Every CS Edge in Slave CON Mode
pub fn txundr(&mut self) -> TXUNDR_W<'_>[src]
Bit 9 - Tx Underflow Interrupt Enable
pub fn rxovr(&mut self) -> RXOVR_W<'_>[src]
Bit 10 - Rx Overflow Interrupt Enable
pub fn rdy(&mut self) -> RDY_W<'_>[src]
Bit 11 - Ready Signal Edge Interrupt Enable
pub fn txdone(&mut self) -> TXDONE_W<'_>[src]
Bit 12 - SPI Transmit Done Interrupt Enable
pub fn xfrdone(&mut self) -> XFRDONE_W<'_>[src]
Bit 13 - SPI Transfer Completion Interrupt Enable
pub fn txempty(&mut self) -> TXEMPTY_W<'_>[src]
Bit 14 - Tx FIFO Empty Interrupt Enable
impl W<u16, Reg<u16, _CNT>>[src]
pub fn value(&mut self) -> VALUE_W<'_>[src]
Bits 0:13 - Transfer Byte Count
pub fn framecont(&mut self) -> FRAMECONT_W<'_>[src]
Bit 15 - Continue Frame
impl W<u16, Reg<u16, _DMA>>[src]
pub fn en(&mut self) -> EN_W<'_>[src]
Bit 0 - Enable DMA for Data Transfer
pub fn txen(&mut self) -> TXEN_W<'_>[src]
Bit 1 - Enable Transmit DMA Request
pub fn rxen(&mut self) -> RXEN_W<'_>[src]
Bit 2 - Enable Receive DMA Request
impl W<u16, Reg<u16, _RD_CTL>>[src]
pub fn cmden(&mut self) -> CMDEN_W<'_>[src]
Bit 0 - Read Command Enable
pub fn overlap(&mut self) -> OVERLAP_W<'_>[src]
Bit 1 - Tx/Rx Overlap Mode
pub fn txbytes(&mut self) -> TXBYTES_W<'_>[src]
Bits 2:5 - Transmit Byte Count - 1 (Read Command)
pub fn threepin(&mut self) -> THREEPIN_W<'_>[src]
Bit 8 - Three Pin SPI Mode
impl W<u16, Reg<u16, _FLOW_CTL>>[src]
pub fn mode(&mut self) -> MODE_W<'_>[src]
Bits 0:1 - Flow Control Mode
pub fn rdypol(&mut self) -> RDYPOL_W<'_>[src]
Bit 4 - Polarity of RDY/MISO Line
pub fn rdburstsz(&mut self) -> RDBURSTSZ_W<'_>[src]
Bits 8:11 - Read Data Burst Size - 1
impl W<u16, Reg<u16, _WAIT_TMR>>[src]
impl W<u16, Reg<u16, _CS_CTL>>[src]
impl W<u16, Reg<u16, _CS_OVERRIDE>>[src]
impl W<u16, Reg<u16, _TX>>[src]
impl W<u16, Reg<u16, _IEN>>[src]
pub fn erbfi(&mut self) -> ERBFI_W<'_>[src]
Bit 0 - Receive Buffer Full Interrupt
pub fn etbei(&mut self) -> ETBEI_W<'_>[src]
Bit 1 - Transmit Buffer Empty Interrupt
pub fn elsi(&mut self) -> ELSI_W<'_>[src]
Bit 2 - Rx Status Interrupt
pub fn edssi(&mut self) -> EDSSI_W<'_>[src]
Bit 3 - Modem Status Interrupt
pub fn edmat(&mut self) -> EDMAT_W<'_>[src]
Bit 4 - DMA Requests in Transmit Mode
pub fn edmar(&mut self) -> EDMAR_W<'_>[src]
Bit 5 - DMA Requests in Receive Mode
impl W<u16, Reg<u16, _LCR>>[src]
pub fn wls(&mut self) -> WLS_W<'_>[src]
Bits 0:1 - Word Length Select
pub fn stop(&mut self) -> STOP_W<'_>[src]
Bit 2 - Stop Bit
pub fn pen(&mut self) -> PEN_W<'_>[src]
Bit 3 - Parity Enable
pub fn eps(&mut self) -> EPS_W<'_>[src]
Bit 4 - Parity Select
pub fn sp(&mut self) -> SP_W<'_>[src]
Bit 5 - Stick Parity
pub fn brk(&mut self) -> BRK_W<'_>[src]
Bit 6 - Set Break
impl W<u16, Reg<u16, _MCR>>[src]
pub fn dtr(&mut self) -> DTR_W<'_>[src]
Bit 0 - Data Terminal Ready
pub fn rts(&mut self) -> RTS_W<'_>[src]
Bit 1 - Request to Send
pub fn out1(&mut self) -> OUT1_W<'_>[src]
Bit 2 - Output 1
pub fn out2(&mut self) -> OUT2_W<'_>[src]
Bit 3 - Output 2
pub fn loopback(&mut self) -> LOOPBACK_W<'_>[src]
Bit 4 - Loopback Mode
impl W<u16, Reg<u16, _SCR>>[src]
impl W<u16, Reg<u16, _FCR>>[src]
pub fn fifoen(&mut self) -> FIFOEN_W<'_>[src]
Bit 0 - FIFO Enable as to Work in 16550 Mode
pub fn rfclr(&mut self) -> RFCLR_W<'_>[src]
Bit 1 - Clear Rx FIFO
pub fn tfclr(&mut self) -> TFCLR_W<'_>[src]
Bit 2 - Clear Tx FIFO
pub fn fdmamd(&mut self) -> FDMAMD_W<'_>[src]
Bit 3 - FIFO DMA Mode
pub fn rftrig(&mut self) -> RFTRIG_W<'_>[src]
Bits 6:7 - Rx FIFO Trigger Level
impl W<u16, Reg<u16, _FBR>>[src]
pub fn divn(&mut self) -> DIVN_W<'_>[src]
Bits 0:10 - Fractional Baud Rate N Divide Bits 0 to 2047
pub fn divm(&mut self) -> DIVM_W<'_>[src]
Bits 11:12 - Fractional Baud Rate M Divide Bits 1 to 3
pub fn fben(&mut self) -> FBEN_W<'_>[src]
Bit 15 - Fractional Baud Rate Generator Enable
impl W<u16, Reg<u16, _DIV>>[src]
impl W<u16, Reg<u16, _LCR2>>[src]
impl W<u16, Reg<u16, _CTL>>[src]
pub fn forceclk(&mut self) -> FORCECLK_W<'_>[src]
Bit 1 - Force UCLK on
pub fn rxinv(&mut self) -> RXINV_W<'_>[src]
Bit 4 - Invert Receiver Line
impl W<u16, Reg<u16, _RSC>>[src]
pub fn oenp(&mut self) -> OENP_W<'_>[src]
Bit 0 - SOUT_EN Polarity
pub fn oensp(&mut self) -> OENSP_W<'_>[src]
Bit 1 - SOUT_EN De-assert Before Full Stop Bit(s)
pub fn disrx(&mut self) -> DISRX_W<'_>[src]
Bit 2 - Disable Rx When Transmitting
pub fn distx(&mut self) -> DISTX_W<'_>[src]
Bit 3 - Hold off Tx When Receiving
impl W<u16, Reg<u16, _ACR>>[src]
pub fn abe(&mut self) -> ABE_W<'_>[src]
Bit 0 - Auto Baud Enable
pub fn dnien(&mut self) -> DNIEN_W<'_>[src]
Bit 1 - Enable Done Interrupt
pub fn toien(&mut self) -> TOIEN_W<'_>[src]
Bit 2 - Enable Time-out Interrupt
pub fn sec(&mut self) -> SEC_W<'_>[src]
Bits 4:6 - Starting Edge Count
pub fn eec(&mut self) -> EEC_W<'_>[src]
Bits 8:11 - Ending Edge Count
impl W<u16, Reg<u16, _CFG>>[src]
pub fn seqrepeat(&mut self) -> SEQREPEAT_W<'_>[src]
Bits 0:7 - Beeper Sequence Repeat Value
pub fn en(&mut self) -> EN_W<'_>[src]
Bit 8 - Beeper Enable
pub fn astartirq(&mut self) -> ASTARTIRQ_W<'_>[src]
Bit 10 - Tone A Start IRQ
pub fn aendirq(&mut self) -> AENDIRQ_W<'_>[src]
Bit 11 - Tone A End IRQ
pub fn bstartirq(&mut self) -> BSTARTIRQ_W<'_>[src]
Bit 12 - Tone B Start IRQ
pub fn bendirq(&mut self) -> BENDIRQ_W<'_>[src]
Bit 13 - Tone B End IRQ
pub fn seqnearendirq(&mut self) -> SEQNEARENDIRQ_W<'_>[src]
Bit 14 - Sequence 1 Cycle from End IRQ
pub fn seqatendirq(&mut self) -> SEQATENDIRQ_W<'_>[src]
Bit 15 - Sequence End IRQ
impl W<u16, Reg<u16, _STAT>>[src]
pub fn astarted(&mut self) -> ASTARTED_W<'_>[src]
Bit 10 - Tone A Has Started
pub fn aended(&mut self) -> AENDED_W<'_>[src]
Bit 11 - Tone A Has Ended
pub fn bstarted(&mut self) -> BSTARTED_W<'_>[src]
Bit 12 - Tone B Has Started
pub fn bended(&mut self) -> BENDED_W<'_>[src]
Bit 13 - Tone B Has Ended
pub fn seqnearend(&mut self) -> SEQNEAREND_W<'_>[src]
Bit 14 - Sequencer Last Tone-pair Has Started
pub fn seqended(&mut self) -> SEQENDED_W<'_>[src]
Bit 15 - Sequencer Has Ended
impl W<u16, Reg<u16, _TONEA>>[src]
pub fn dur(&mut self) -> DUR_W<'_>[src]
Bits 0:7 - Tone Duration
pub fn freq(&mut self) -> FREQ_W<'_>[src]
Bits 8:14 - Tone Frequency
pub fn dis(&mut self) -> DIS_W<'_>[src]
Bit 15 - Output Disable
impl W<u16, Reg<u16, _TONEB>>[src]
pub fn dur(&mut self) -> DUR_W<'_>[src]
Bits 0:7 - Tone Duration
pub fn freq(&mut self) -> FREQ_W<'_>[src]
Bits 8:14 - Tone Frequency
pub fn dis(&mut self) -> DIS_W<'_>[src]
Bit 15 - Output Disable
impl W<u16, Reg<u16, _CFG>>[src]
pub fn pwrup(&mut self) -> PWRUP_W<'_>[src]
Bit 0 - Powering up the ADC
pub fn vrefsel(&mut self) -> VREFSEL_W<'_>[src]
Bit 1 - Select Vref as 1.25V or 2.5V
pub fn refbufen(&mut self) -> REFBUFEN_W<'_>[src]
Bit 2 - Enable Internal Reference Buffer
pub fn en(&mut self) -> EN_W<'_>[src]
Bit 4 - Enable ADC Subsystem
pub fn startcal(&mut self) -> STARTCAL_W<'_>[src]
Bit 5 - Start a New Offset Calibration Cycle
pub fn rst(&mut self) -> RST_W<'_>[src]
Bit 6 - Reset
pub fn sinken(&mut self) -> SINKEN_W<'_>[src]
Bit 7 - Enable Additional Sink Current Capability
pub fn tmpen(&mut self) -> TMPEN_W<'_>[src]
Bit 8 - Power up Temperature Sensor
pub fn fast_disch(&mut self) -> FAST_DISCH_W<'_>[src]
Bit 9 - Fast Switchover of Vref from 2.5 to 1.25
impl W<u16, Reg<u16, _PWRUP>>[src]
impl W<u16, Reg<u16, _CAL_WORD>>[src]
impl W<u16, Reg<u16, _CNV_CFG>>[src]
pub fn sel(&mut self) -> SEL_W<'_>[src]
Bits 0:7 - Selection of Channel(s) to Convert
pub fn bat(&mut self) -> BAT_W<'_>[src]
Bit 8 - Battery Monitoring Enable
pub fn tmp(&mut self) -> TMP_W<'_>[src]
Bit 9 - Temperature Measurement 1
pub fn tmp2(&mut self) -> TMP2_W<'_>[src]
Bit 10 - Temperature Measurement 2
pub fn automode(&mut self) -> AUTOMODE_W<'_>[src]
Bit 12 - Auto Mode Enable
pub fn dmaen(&mut self) -> DMAEN_W<'_>[src]
Bit 13 - DMA Channel Enable
pub fn single(&mut self) -> SINGLE_W<'_>[src]
Bit 14 - Single Conversion Start
pub fn multi(&mut self) -> MULTI_W<'_>[src]
Bit 15 - Multiple Conversions
impl W<u16, Reg<u16, _CNV_TIME>>[src]
pub fn samptime(&mut self) -> SAMPTIME_W<'_>[src]
Bits 0:7 - Sampling Time
pub fn dly(&mut self) -> DLY_W<'_>[src]
Bits 8:15 - Delay Between Two Consecutive Conversions
impl W<u16, Reg<u16, _AVG_CFG>>[src]
pub fn factor(&mut self) -> FACTOR_W<'_>[src]
Bits 0:7 - Averaging Factor
pub fn os(&mut self) -> OS_W<'_>[src]
Bit 14 - Enable Oversampling
pub fn en(&mut self) -> EN_W<'_>[src]
Bit 15 - Enable Averaging on Channels Enabled in Enable Register
impl W<u16, Reg<u16, _IRQ_EN>>[src]
pub fn cnvdone(&mut self) -> CNVDONE_W<'_>[src]
Bit 0 - Enable Conversion Done Interrupt
pub fn caldone(&mut self) -> CALDONE_W<'_>[src]
Bit 10 - Enable Interrupt for Calibration Done
pub fn ovf(&mut self) -> OVF_W<'_>[src]
Bit 11 - Enable Overflow Interrupt
pub fn alert(&mut self) -> ALERT_W<'_>[src]
Bit 12 - Interrupt on Crossing Lower or Higher Limit Enable
pub fn rdy(&mut self) -> RDY_W<'_>[src]
Bit 13 - Set to Enable Interrupt When ADC is Ready to Convert
impl W<u16, Reg<u16, _STAT>>[src]
pub fn done0(&mut self) -> DONE0_W<'_>[src]
Bit 0 - Conversion Done on Channel 0
pub fn done1(&mut self) -> DONE1_W<'_>[src]
Bit 1 - Conversion Done on Channel 1
pub fn done2(&mut self) -> DONE2_W<'_>[src]
Bit 2 - Conversion Done on Channel 2
pub fn done3(&mut self) -> DONE3_W<'_>[src]
Bit 3 - Conversion Done on Channel 3
pub fn done4(&mut self) -> DONE4_W<'_>[src]
Bit 4 - Conversion Done on Channel 4
pub fn done5(&mut self) -> DONE5_W<'_>[src]
Bit 5 - Conversion Done on Channel 5
pub fn done6(&mut self) -> DONE6_W<'_>[src]
Bit 6 - Conversion Done on Channel 6
pub fn done7(&mut self) -> DONE7_W<'_>[src]
Bit 7 - Conversion Done on Channel 7
pub fn batdone(&mut self) -> BATDONE_W<'_>[src]
Bit 8 - Conversion Done - Battery Monitoring
pub fn tmpdone(&mut self) -> TMPDONE_W<'_>[src]
Bit 9 - Conversion Done for Temperature Sensing
pub fn tmp2done(&mut self) -> TMP2DONE_W<'_>[src]
Bit 10 - Conversion Done for Temperature Sensing 2
pub fn caldone(&mut self) -> CALDONE_W<'_>[src]
Bit 14 - Calibration Done
pub fn rdy(&mut self) -> RDY_W<'_>[src]
Bit 15 - ADC Ready to Start Converting
impl W<u16, Reg<u16, _OVF>>[src]
pub fn ch0(&mut self) -> CH0_W<'_>[src]
Bit 0 - Overflow in CH0_OUT
pub fn ch1(&mut self) -> CH1_W<'_>[src]
Bit 1 - Overflow in CH1_OUT
pub fn ch2(&mut self) -> CH2_W<'_>[src]
Bit 2 - Overflow in CH2_OUT
pub fn ch3(&mut self) -> CH3_W<'_>[src]
Bit 3 - Overflow in CH3_OUT
pub fn ch4(&mut self) -> CH4_W<'_>[src]
Bit 4 - Overflow in CH4_OUT
pub fn ch5(&mut self) -> CH5_W<'_>[src]
Bit 5 - Overflow in CH5_OUT
pub fn ch6(&mut self) -> CH6_W<'_>[src]
Bit 6 - Overflow in CH6_OUT
pub fn ch7(&mut self) -> CH7_W<'_>[src]
Bit 7 - Overflow in CH7_OUT
pub fn bat(&mut self) -> BAT_W<'_>[src]
Bit 8 - Overflow in BAT_OUT
pub fn tmp(&mut self) -> TMP_W<'_>[src]
Bit 9 - Overflow in TMP_OUT
pub fn tmp2(&mut self) -> TMP2_W<'_>[src]
Bit 10 - Overflow in TMP2_OUT
impl W<u16, Reg<u16, _ALERT>>[src]
pub fn hi0(&mut self) -> HI0_W<'_>[src]
Bit 0 - Channel 0 High Alert Status
pub fn lo0(&mut self) -> LO0_W<'_>[src]
Bit 1 - Channel 0 Low Alert Status
pub fn hi1(&mut self) -> HI1_W<'_>[src]
Bit 2 - Channel 1 High Alert Status
pub fn lo1(&mut self) -> LO1_W<'_>[src]
Bit 3 - Channel 1 Low Alert Status
pub fn hi2(&mut self) -> HI2_W<'_>[src]
Bit 4 - Channel 2 High Alert Status
pub fn lo2(&mut self) -> LO2_W<'_>[src]
Bit 5 - Channel 2 Low Alert Status
pub fn hi3(&mut self) -> HI3_W<'_>[src]
Bit 6 - Channel 3 High Alert Status
pub fn lo3(&mut self) -> LO3_W<'_>[src]
Bit 7 - Channel 3 Low Alert Status
impl W<u16, Reg<u16, _LIM0_LO>>[src]
pub fn value(&mut self) -> VALUE_W<'_>[src]
Bits 0:11 - Low Limit for Channel 0
pub fn en(&mut self) -> EN_W<'_>[src]
Bit 15 - Enable Low Limit Comparison on Channel 0
impl W<u16, Reg<u16, _LIM0_HI>>[src]
pub fn value(&mut self) -> VALUE_W<'_>[src]
Bits 0:11 - High Limit for Channel 0
pub fn en(&mut self) -> EN_W<'_>[src]
Bit 15 - Enable High Limit Comparison on Channel 0
impl W<u16, Reg<u16, _HYS0>>[src]
pub fn value(&mut self) -> VALUE_W<'_>[src]
Bits 0:8 - Hysteresis Value for Channel 0
pub fn moncyc(&mut self) -> MONCYC_W<'_>[src]
Bits 12:14 - Number of Conversion Cycles to Monitor Channel 0
pub fn en(&mut self) -> EN_W<'_>[src]
Bit 15 - Enable Hysteresis for Comparison on Channel 0
impl W<u16, Reg<u16, _LIM1_LO>>[src]
pub fn value(&mut self) -> VALUE_W<'_>[src]
Bits 0:11 - Low Limit for Channel 1
pub fn en(&mut self) -> EN_W<'_>[src]
Bit 15 - Enable Low Limit Comparison on Channel 1
impl W<u16, Reg<u16, _LIM1_HI>>[src]
pub fn value(&mut self) -> VALUE_W<'_>[src]
Bits 0:11 - High Limit for Channel 1
pub fn en(&mut self) -> EN_W<'_>[src]
Bit 15 - Enable High Limit Comparison on Channel 1
impl W<u16, Reg<u16, _HYS1>>[src]
pub fn value(&mut self) -> VALUE_W<'_>[src]
Bits 0:8 - Hysteresis Value for Channel 1
pub fn moncyc(&mut self) -> MONCYC_W<'_>[src]
Bits 12:14 - Number of Conversion Cycles to Monitor Channel 1
pub fn en(&mut self) -> EN_W<'_>[src]
Bit 15 - Enable Hysteresis for Comparison on Channel 1
impl W<u16, Reg<u16, _LIM2_LO>>[src]
pub fn value(&mut self) -> VALUE_W<'_>[src]
Bits 0:11 - Low Limit for Channel 2
pub fn en(&mut self) -> EN_W<'_>[src]
Bit 15 - Enable Low Limit Comparison on Channel 2
impl W<u16, Reg<u16, _LIM2_HI>>[src]
pub fn value(&mut self) -> VALUE_W<'_>[src]
Bits 0:11 - High Limit for Channel 2
pub fn en(&mut self) -> EN_W<'_>[src]
Bit 15 - Enable High Limit Comparison on Channel
impl W<u16, Reg<u16, _HYS2>>[src]
pub fn value(&mut self) -> VALUE_W<'_>[src]
Bits 0:8 - Hysteresis Value for Channel 2
pub fn moncyc(&mut self) -> MONCYC_W<'_>[src]
Bits 12:14 - Number of Conversion Cycles to Monitor Channel 2
pub fn en(&mut self) -> EN_W<'_>[src]
Bit 15 - Enable Hysteresis for Comparison on Channel 2
impl W<u16, Reg<u16, _LIM3_LO>>[src]
pub fn value(&mut self) -> VALUE_W<'_>[src]
Bits 0:11 - Low Limit for Channel 3
pub fn en(&mut self) -> EN_W<'_>[src]
Bit 15 - Enable Low Limit Comparison on Channel 3
impl W<u16, Reg<u16, _LIM3_HI>>[src]
pub fn value(&mut self) -> VALUE_W<'_>[src]
Bits 0:11 - High Limit for Channel 3
pub fn en(&mut self) -> EN_W<'_>[src]
Bit 15 - Enable High Limit Comparison on Channel 3
impl W<u16, Reg<u16, _HYS3>>[src]
pub fn value(&mut self) -> VALUE_W<'_>[src]
Bits 0:8 - Hysteresis Value for Channel 3
pub fn moncyc(&mut self) -> MONCYC_W<'_>[src]
Bits 12:14 - Number of Conversion Cycles to Monitor Channel 3
pub fn en(&mut self) -> EN_W<'_>[src]
Bit 15 - Enable Hysteresis for Comparison on Channel 3
impl W<u16, Reg<u16, _CFG1>>[src]
impl W<u32, Reg<u32, _CFG>>[src]
impl W<u32, Reg<u32, _PDBPTR>>[src]
pub fn addr(&mut self) -> ADDR_W<'_>[src]
Bits 0:31 - Pointer to the Base Address of the Primary Data Structure
impl W<u32, Reg<u32, _SWREQ>>[src]
impl W<u32, Reg<u32, _RMSK_SET>>[src]
impl W<u32, Reg<u32, _RMSK_CLR>>[src]
impl W<u32, Reg<u32, _EN_SET>>[src]
impl W<u32, Reg<u32, _EN_CLR>>[src]
impl W<u32, Reg<u32, _ALT_SET>>[src]
pub fn chan(&mut self) -> CHAN_W<'_>[src]
Bits 0:24 - Control Structure Status / Select Alternate Structure
impl W<u32, Reg<u32, _ALT_CLR>>[src]
impl W<u32, Reg<u32, _PRI_SET>>[src]
impl W<u32, Reg<u32, _PRI_CLR>>[src]
pub fn chpriclr(&mut self) -> CHPRICLR_W<'_>[src]
Bits 0:24 - Configure Channel for Default Priority Level
impl W<u32, Reg<u32, _ERRCHNL_CLR>>[src]
impl W<u32, Reg<u32, _ERR_CLR>>[src]
impl W<u32, Reg<u32, _INVALIDDESC_CLR>>[src]
impl W<u32, Reg<u32, _BS_SET>>[src]
impl W<u32, Reg<u32, _BS_CLR>>[src]
impl W<u32, Reg<u32, _SRCADDR_SET>>[src]
impl W<u32, Reg<u32, _SRCADDR_CLR>>[src]
impl W<u32, Reg<u32, _DSTADDR_SET>>[src]
impl W<u32, Reg<u32, _DSTADDR_CLR>>[src]
impl W<u32, Reg<u32, _STAT>>[src]
impl W<u32, Reg<u32, _IEN>>[src]
pub fn cmdcmplt(&mut self) -> CMDCMPLT_W<'_>[src]
Bit 0 - Command Complete Interrupt Enable
pub fn wralcmplt(&mut self) -> WRALCMPLT_W<'_>[src]
Bit 1 - Write Almost Complete Interrupt Enable
pub fn cmdfail(&mut self) -> CMDFAIL_W<'_>[src]
Bit 2 - Command Fail Interrupt Enable
pub fn ecc_error(&mut self) -> ECC_ERROR_W<'_>[src]
Bits 6:7 - Control 2-bit ECC Error Events
impl W<u32, Reg<u32, _CMD>>[src]
impl W<u32, Reg<u32, _KH_ADDR>>[src]
impl W<u32, Reg<u32, _KH_DATA0>>[src]
impl W<u32, Reg<u32, _KH_DATA1>>[src]
pub fn value(&mut self) -> VALUE_W<'_>[src]
Bits 0:31 - Upper Half of 64-bit Dualword Data to Be Written
impl W<u32, Reg<u32, _PAGE_ADDR0>>[src]
impl W<u32, Reg<u32, _PAGE_ADDR1>>[src]
impl W<u32, Reg<u32, _KEY>>[src]
impl W<u32, Reg<u32, _WRPROT>>[src]
impl W<u32, Reg<u32, _UCFG>>[src]
pub fn khdmaen(&mut self) -> KHDMAEN_W<'_>[src]
Bit 0 - Key Hole DMA Enable
pub fn autoincen(&mut self) -> AUTOINCEN_W<'_>[src]
Bit 1 - Auto Address Increment for Key Hole Access
impl W<u32, Reg<u32, _TIME_PARAM0>>[src]
pub fn divrefclk(&mut self) -> DIVREFCLK_W<'_>[src]
Bit 0 - Divide Reference Clock (by 2)
pub fn tnvs(&mut self) -> TNVS_W<'_>[src]
Bits 4:7 - PROG/ERASE to NVSTR Setup Time
pub fn tpgs(&mut self) -> TPGS_W<'_>[src]
Bits 8:11 - NVSTR to Program Setup Time
pub fn tprog(&mut self) -> TPROG_W<'_>[src]
Bits 12:15 - Program Time
pub fn tnvh(&mut self) -> TNVH_W<'_>[src]
Bits 16:19 - NVSTR Hold Time
pub fn trcv(&mut self) -> TRCV_W<'_>[src]
Bits 20:23 - Recovery Time
pub fn terase(&mut self) -> TERASE_W<'_>[src]
Bits 24:27 - Erase Time
pub fn tnvh1(&mut self) -> TNVH1_W<'_>[src]
Bits 28:31 - NVSTR Hold Time During Mass Erase
impl W<u32, Reg<u32, _TIME_PARAM1>>[src]
impl W<u32, Reg<u32, _ABORT_EN_LO>>[src]
impl W<u32, Reg<u32, _ABORT_EN_HI>>[src]
impl W<u32, Reg<u32, _ECC_CFG>>[src]
pub fn en(&mut self) -> EN_W<'_>[src]
Bit 0 - ECC Enable
pub fn infoen(&mut self) -> INFOEN_W<'_>[src]
Bit 1 - Info Space ECC Enable Bit
pub fn ptr(&mut self) -> PTR_W<'_>[src]
Bits 8:31 - ECC Start Page Pointer
impl W<u32, Reg<u32, _POR_SEC>>[src]
pub fn secure(&mut self) -> SECURE_W<'_>[src]
Bit 0 - Prevent Read/Write Access to User Space (Sticky When Set)
impl W<u32, Reg<u32, _VOL_CFG>>[src]
pub fn info_remap(&mut self) -> INFO_REMAP_W<'_>[src]
Bit 0 - Alias the Info Space to the Base Address of User Space
impl W<u32, Reg<u32, _SETUP>>[src]
impl W<u32, Reg<u32, _KEY>>[src]
impl W<u32, Reg<u32, _CFG>>[src]
pub fn pin00(&mut self) -> PIN00_W<'_>[src]
Bits 0:1 - Pin 0 Configuration Bits
pub fn pin01(&mut self) -> PIN01_W<'_>[src]
Bits 2:3 - Pin 1 Configuration Bits
pub fn pin02(&mut self) -> PIN02_W<'_>[src]
Bits 4:5 - Pin 2 Configuration Bits
pub fn pin03(&mut self) -> PIN03_W<'_>[src]
Bits 6:7 - Pin 3 Configuration Bits
pub fn pin04(&mut self) -> PIN04_W<'_>[src]
Bits 8:9 - Pin 4 Configuration Bits
pub fn pin05(&mut self) -> PIN05_W<'_>[src]
Bits 10:11 - Pin 5 Configuration Bits
pub fn pin06(&mut self) -> PIN06_W<'_>[src]
Bits 12:13 - Pin 6 Configuration Bits
pub fn pin07(&mut self) -> PIN07_W<'_>[src]
Bits 14:15 - Pin 7 Configuration Bits
pub fn pin08(&mut self) -> PIN08_W<'_>[src]
Bits 16:17 - Pin 8 Configuration Bits
pub fn pin09(&mut self) -> PIN09_W<'_>[src]
Bits 18:19 - Pin 9 Configuration Bits
pub fn pin10(&mut self) -> PIN10_W<'_>[src]
Bits 20:21 - Pin 10 Configuration Bits
pub fn pin11(&mut self) -> PIN11_W<'_>[src]
Bits 22:23 - Pin 11 Configuration Bits
pub fn pin12(&mut self) -> PIN12_W<'_>[src]
Bits 24:25 - Pin 12 Configuration Bits
pub fn pin13(&mut self) -> PIN13_W<'_>[src]
Bits 26:27 - Pin 13 Configuration Bits
pub fn pin14(&mut self) -> PIN14_W<'_>[src]
Bits 28:29 - Pin 14 Configuration Bits
pub fn pin15(&mut self) -> PIN15_W<'_>[src]
Bits 30:31 - Pin 15 Configuration Bits
impl W<u16, Reg<u16, _OEN>>[src]
impl W<u16, Reg<u16, _PE>>[src]
impl W<u16, Reg<u16, _IEN>>[src]
impl W<u16, Reg<u16, _OUT>>[src]
impl W<u16, Reg<u16, _SET>>[src]
impl W<u16, Reg<u16, _CLR>>[src]
impl W<u16, Reg<u16, _TGL>>[src]
impl W<u16, Reg<u16, _POL>>[src]
impl W<u16, Reg<u16, _IENA>>[src]
impl W<u16, Reg<u16, _IENB>>[src]
impl W<u16, Reg<u16, _INT>>[src]
impl W<u16, Reg<u16, _DS>>[src]
pub fn pin00(&mut self) -> PIN00_W<'_>[src]
Bit 0 - Drive Strength Pin 00
pub fn pin01(&mut self) -> PIN01_W<'_>[src]
Bit 1 - Drive Strength Pin 01
pub fn pin02(&mut self) -> PIN02_W<'_>[src]
Bit 2 - Drive Strength Pin 02
pub fn pin03(&mut self) -> PIN03_W<'_>[src]
Bit 3 - Drive Strength Pin 03
pub fn pin04(&mut self) -> PIN04_W<'_>[src]
Bit 4 - Drive Strength Pin 04
pub fn pin05(&mut self) -> PIN05_W<'_>[src]
Bit 5 - Drive Strength Pin 05
pub fn pin06(&mut self) -> PIN06_W<'_>[src]
Bit 6 - Drive Strength Pin 06
pub fn pin07(&mut self) -> PIN07_W<'_>[src]
Bit 7 - Drive Strength Pin 07
pub fn pin08(&mut self) -> PIN08_W<'_>[src]
Bit 8 - Drive Strength Pin 08
pub fn pin09(&mut self) -> PIN09_W<'_>[src]
Bit 9 - Drive Strength Pin 09
pub fn pin10(&mut self) -> PIN10_W<'_>[src]
Bit 10 - Drive Strength Pin 10
pub fn pin11(&mut self) -> PIN11_W<'_>[src]
Bit 11 - Drive Strength Pin 11
pub fn pin12(&mut self) -> PIN12_W<'_>[src]
Bit 12 - Drive Strength Pin 12
pub fn pin13(&mut self) -> PIN13_W<'_>[src]
Bit 13 - Drive Strength Pin 13
pub fn pin14(&mut self) -> PIN14_W<'_>[src]
Bit 14 - Drive Strength Pin 14
pub fn pin15(&mut self) -> PIN15_W<'_>[src]
Bit 15 - Drive Strength Pin 15
impl W<u32, Reg<u32, _CTL_A>>[src]
pub fn spen(&mut self) -> SPEN_W<'_>[src]
Bit 0 - Serial Port Enable
pub fn fsmuxsel(&mut self) -> FSMUXSEL_W<'_>[src]
Bit 1 - Frame Sync Multiplexer Select
pub fn ckmuxsel(&mut self) -> CKMUXSEL_W<'_>[src]
Bit 2 - Clock Multiplexer Select
pub fn lsbf(&mut self) -> LSBF_W<'_>[src]
Bit 3 - Least-Significant Bit First
pub fn slen(&mut self) -> SLEN_W<'_>[src]
Bits 4:8 - Serial Word Length
pub fn iclk(&mut self) -> ICLK_W<'_>[src]
Bit 10 - Internal Clock
pub fn opmode(&mut self) -> OPMODE_W<'_>[src]
Bit 11 - Operation Mode
pub fn ckre(&mut self) -> CKRE_W<'_>[src]
Bit 12 - Clock Rising Edge
pub fn fsr(&mut self) -> FSR_W<'_>[src]
Bit 13 - Frame Sync Required
pub fn ifs(&mut self) -> IFS_W<'_>[src]
Bit 14 - Internal Frame Sync
pub fn difs(&mut self) -> DIFS_W<'_>[src]
Bit 15 - Data-Independent Frame Sync
pub fn lfs(&mut self) -> LFS_W<'_>[src]
Bit 16 - Active-Low Frame Sync
pub fn lafs(&mut self) -> LAFS_W<'_>[src]
Bit 17 - Late Frame Sync
pub fn pack(&mut self) -> PACK_W<'_>[src]
Bits 18:19 - Packing Enable
pub fn fserrmode(&mut self) -> FSERRMODE_W<'_>[src]
Bit 20 - Frame Sync Error Operation
pub fn gclken(&mut self) -> GCLKEN_W<'_>[src]
Bit 21 - Gated Clock Enable
pub fn sptran(&mut self) -> SPTRAN_W<'_>[src]
Bit 25 - Serial Port Transfer Direction
pub fn dmaen(&mut self) -> DMAEN_W<'_>[src]
Bit 26 - DMA Enable
impl W<u32, Reg<u32, _DIV_A>>[src]
pub fn clkdiv(&mut self) -> CLKDIV_W<'_>[src]
Bits 0:15 - Clock Divisor
pub fn fsdiv(&mut self) -> FSDIV_W<'_>[src]
Bits 16:23 - Frame Sync Divisor
impl W<u32, Reg<u32, _IEN_A>>[src]
pub fn tf(&mut self) -> TF_W<'_>[src]
Bit 0 - Transfer Finish Interrupt Enable
pub fn derrmsk(&mut self) -> DERRMSK_W<'_>[src]
Bit 1 - Data Error (Interrupt) Mask
pub fn fserrmsk(&mut self) -> FSERRMSK_W<'_>[src]
Bit 2 - Frame Sync Error (Interrupt) Mask
pub fn data(&mut self) -> DATA_W<'_>[src]
Bit 3 - Data Request Interrupt to the Core
pub fn sysdaterr(&mut self) -> SYSDATERR_W<'_>[src]
Bit 4 - Data Error for System Writes or Reads
impl W<u32, Reg<u32, _NUMTRAN_A>>[src]
impl W<u32, Reg<u32, _CNVT_A>>[src]
pub fn wid(&mut self) -> WID_W<'_>[src]
Bits 0:3 - SPT_CNVT Signal Width: Half SPORT a
pub fn pol(&mut self) -> POL_W<'_>[src]
Bit 8 - Polarity of the SPT_CNVT Signal
pub fn cnvt2fs(&mut self) -> CNVT2FS_W<'_>[src]
Bits 16:23 - SPT_CNVT to FS Duration: Half SPORT a
impl W<u32, Reg<u32, _TX_A>>[src]
impl W<u32, Reg<u32, _CTL_B>>[src]
pub fn spen(&mut self) -> SPEN_W<'_>[src]
Bit 0 - Serial Port Enable
pub fn lsbf(&mut self) -> LSBF_W<'_>[src]
Bit 3 - Least-Significant Bit First
pub fn slen(&mut self) -> SLEN_W<'_>[src]
Bits 4:8 - Serial Word Length
pub fn iclk(&mut self) -> ICLK_W<'_>[src]
Bit 10 - Internal Clock
pub fn opmode(&mut self) -> OPMODE_W<'_>[src]
Bit 11 - Operation Mode
pub fn ckre(&mut self) -> CKRE_W<'_>[src]
Bit 12 - Clock Rising Edge
pub fn fsr(&mut self) -> FSR_W<'_>[src]
Bit 13 - Frame Sync Required
pub fn ifs(&mut self) -> IFS_W<'_>[src]
Bit 14 - Internal Frame Sync
pub fn difs(&mut self) -> DIFS_W<'_>[src]
Bit 15 - Data-Independent Frame Sync
pub fn lfs(&mut self) -> LFS_W<'_>[src]
Bit 16 - Active-Low Frame Sync
pub fn lafs(&mut self) -> LAFS_W<'_>[src]
Bit 17 - Late Frame Sync
pub fn pack(&mut self) -> PACK_W<'_>[src]
Bits 18:19 - Packing Enable
pub fn fserrmode(&mut self) -> FSERRMODE_W<'_>[src]
Bit 20 - Frame Sync Error Operation
pub fn gclken(&mut self) -> GCLKEN_W<'_>[src]
Bit 21 - Gated Clock Enable
pub fn sptran(&mut self) -> SPTRAN_W<'_>[src]
Bit 25 - Serial Port Transfer Direction
pub fn dmaen(&mut self) -> DMAEN_W<'_>[src]
Bit 26 - DMA Enable
impl W<u32, Reg<u32, _DIV_B>>[src]
pub fn clkdiv(&mut self) -> CLKDIV_W<'_>[src]
Bits 0:15 - Clock Divisor
pub fn fsdiv(&mut self) -> FSDIV_W<'_>[src]
Bits 16:23 - Frame Sync Divisor
impl W<u32, Reg<u32, _IEN_B>>[src]
pub fn tf(&mut self) -> TF_W<'_>[src]
Bit 0 - Transmit Finish Interrupt Enable
pub fn derrmsk(&mut self) -> DERRMSK_W<'_>[src]
Bit 1 - Data Error (Interrupt) Mask
pub fn fserrmsk(&mut self) -> FSERRMSK_W<'_>[src]
Bit 2 - Frame Sync Error (Interrupt) Mask
pub fn data(&mut self) -> DATA_W<'_>[src]
Bit 3 - Data Request Interrupt to the Core
pub fn sysdaterr(&mut self) -> SYSDATERR_W<'_>[src]
Bit 4 - Data Error for System Writes or Reads
impl W<u32, Reg<u32, _NUMTRAN_B>>[src]
impl W<u32, Reg<u32, _CNVT_B>>[src]
pub fn wid(&mut self) -> WID_W<'_>[src]
Bits 0:3 - SPT_CNVT Signal Width: Half SPORT B
pub fn pol(&mut self) -> POL_W<'_>[src]
Bit 8 - Polarity of the SPT_CNVT Signal
pub fn cnvt2fs(&mut self) -> CNVT2FS_W<'_>[src]
Bits 16:23 - SPT_CNVT to FS Duration: Half SPORT B
impl W<u32, Reg<u32, _TX_B>>[src]
impl W<u32, Reg<u32, _CTL>>[src]
pub fn en(&mut self) -> EN_W<'_>[src]
Bit 0 - CRC Peripheral Enable
pub fn lsbfirst(&mut self) -> LSBFIRST_W<'_>[src]
Bit 1 - LSB First Calculation Order
pub fn bitmirr(&mut self) -> BITMIRR_W<'_>[src]
Bit 2 - Bit Mirroring
pub fn bytmirr(&mut self) -> BYTMIRR_W<'_>[src]
Bit 3 - Byte Mirroring
pub fn w16swp(&mut self) -> W16SWP_W<'_>[src]
Bit 4 - Word16 Swap
impl W<u32, Reg<u32, _IPDATA>>[src]
impl W<u32, Reg<u32, _RESULT>>[src]
impl W<u32, Reg<u32, _POLY>>[src]
impl W<u8, Reg<u8, _IPBITS>>[src]
pub fn data_bits(&mut self) -> DATA_BITS_W<'_>[src]
Bits 0:7 - Input Data Bits
impl W<u8, Reg<u8, _IPBYTE>>[src]
pub fn data_byte(&mut self) -> DATA_BYTE_W<'_>[src]
Bits 0:7 - Input Data Byte
impl W<u16, Reg<u16, _CTL>>[src]
pub fn en(&mut self) -> EN_W<'_>[src]
Bit 0 - RNG Enable
pub fn single(&mut self) -> SINGLE_W<'_>[src]
Bit 3 - Generate a Single Number
impl W<u16, Reg<u16, _LEN>>[src]
pub fn reload(&mut self) -> RELOAD_W<'_>[src]
Bits 0:11 - Reload Value for the Sample Counter
pub fn prescale(&mut self) -> PRESCALE_W<'_>[src]
Bits 12:15 - Prescaler for the Sample Counter
impl W<u16, Reg<u16, _STAT>>[src]
pub fn rnrdy(&mut self) -> RNRDY_W<'_>[src]
Bit 0 - Random Number Ready
pub fn stuck(&mut self) -> STUCK_W<'_>[src]
Bit 1 - Sampled Data Stuck High or Low
impl W<u32, Reg<u32, _CFG>>[src]
pub fn blken(&mut self) -> BLKEN_W<'_>[src]
Bit 0 - Enable Bit for Crypto Block
pub fn encr(&mut self) -> ENCR_W<'_>[src]
Bit 1 - Encrypt or Decrypt
pub fn indmaen(&mut self) -> INDMAEN_W<'_>[src]
Bit 2 - Enable DMA Channel Request for Input Buffer
pub fn outdmaen(&mut self) -> OUTDMAEN_W<'_>[src]
Bit 3 - Enable DMA Channel Request for Output Buffer
pub fn inflush(&mut self) -> INFLUSH_W<'_>[src]
Bit 4 - Input Buffer Flush
pub fn outflush(&mut self) -> OUTFLUSH_W<'_>[src]
Bit 5 - Output Buffer Flush
pub fn aes_byteswap(&mut self) -> AES_BYTESWAP_W<'_>[src]
Bit 6 - Byte Swap 32 Bit AES Input Data
pub fn aeskeylen(&mut self) -> AESKEYLEN_W<'_>[src]
Bits 8:9 - Select Key Length for AES Cipher
pub fn ecben(&mut self) -> ECBEN_W<'_>[src]
Bit 16 - Enable ECB Mode Operation
pub fn ctren(&mut self) -> CTREN_W<'_>[src]
Bit 17 - Enable CTR Mode Operation
pub fn cbcen(&mut self) -> CBCEN_W<'_>[src]
Bit 18 - Enable CBC Mode Operation
pub fn ccmen(&mut self) -> CCMEN_W<'_>[src]
Bit 19 - Enable CCM/CCM* Mode Operation
pub fn cmacen(&mut self) -> CMACEN_W<'_>[src]
Bit 20 - Enable CMAC Mode Operation
pub fn sha256en(&mut self) -> SHA256EN_W<'_>[src]
Bit 25 - Enable SHA-256 Operation
pub fn shainit(&mut self) -> SHAINIT_W<'_>[src]
Bit 26 - Restarts SHA Computation
impl W<u32, Reg<u32, _DATALEN>>[src]
impl W<u32, Reg<u32, _PREFIXLEN>>[src]
impl W<u32, Reg<u32, _INTEN>>[src]
pub fn inrdyen(&mut self) -> INRDYEN_W<'_>[src]
Bit 0 - Enable Input Ready Interrupt
pub fn outrdyen(&mut self) -> OUTRDYEN_W<'_>[src]
Bit 1 - Enables the Output Ready Interrupt
pub fn inovren(&mut self) -> INOVREN_W<'_>[src]
Bit 2 - Enable Input Overflow Interrupt
pub fn shadonen(&mut self) -> SHADONEN_W<'_>[src]
Bit 5 - Enable SHA_Done Interrupt
impl W<u32, Reg<u32, _STAT>>[src]
pub fn inovr(&mut self) -> INOVR_W<'_>[src]
Bit 2 - Overflow in the Input Buffer
pub fn shadone(&mut self) -> SHADONE_W<'_>[src]
Bit 5 - SHA Computation Complete
impl W<u32, Reg<u32, _INBUF>>[src]
impl W<u32, Reg<u32, _NONCE0>>[src]
impl W<u32, Reg<u32, _NONCE1>>[src]
impl W<u32, Reg<u32, _NONCE2>>[src]
impl W<u32, Reg<u32, _NONCE3>>[src]
impl W<u32, Reg<u32, _AESKEY0>>[src]
impl W<u32, Reg<u32, _AESKEY1>>[src]
impl W<u32, Reg<u32, _AESKEY2>>[src]
impl W<u32, Reg<u32, _AESKEY3>>[src]
impl W<u32, Reg<u32, _AESKEY4>>[src]
impl W<u32, Reg<u32, _AESKEY5>>[src]
impl W<u32, Reg<u32, _AESKEY6>>[src]
impl W<u32, Reg<u32, _AESKEY7>>[src]
impl W<u32, Reg<u32, _CNTRINIT>>[src]
impl W<u32, Reg<u32, _SHA_LAST_WORD>>[src]
pub fn o_last_word(&mut self) -> O_LAST_WORD_W<'_>[src]
Bit 0 - Last SHA Input Word
pub fn o_bits_valid(&mut self) -> O_BITS_VALID_W<'_>[src]
Bits 1:5 - Bits Valid in SHA Last Word Input
impl W<u32, Reg<u32, _CCM_NUM_VALID_BYTES>>[src]
pub fn num_valid_bytes(&mut self) -> NUM_VALID_BYTES_W<'_>[src]
Bits 0:3 - Number of Valid Bytes in CCM Last Data
impl W<u32, Reg<u32, _IEN>>[src]
pub fn vbat(&mut self) -> VBAT_W<'_>[src]
Bit 0 - Enable Interrupt for VBAT
pub fn vregundr(&mut self) -> VREGUNDR_W<'_>[src]
Bit 1 - Enable Interrupt When VREG Undervoltage: Below 1V
pub fn vregovr(&mut self) -> VREGOVR_W<'_>[src]
Bit 2 - Enable Interrupt When VREG Overvoltage: Above 1.32V
pub fn rangebat(&mut self) -> RANGEBAT_W<'_>[src]
Bits 8:9 - Battery Monitor Range
pub fn ienbat(&mut self) -> IENBAT_W<'_>[src]
Bit 10 - Interrupt Enable for VBAT Range
impl W<u32, Reg<u32, _PSM_STAT>>[src]
pub fn vbatundr(&mut self) -> VBATUNDR_W<'_>[src]
Bit 0 - Status Bit Indicating an Alarm That Battery is Below 1.8V
pub fn vregundr(&mut self) -> VREGUNDR_W<'_>[src]
Bit 1 - Status Bit for Alarm Indicating VREG is Below 1V
pub fn vregovr(&mut self) -> VREGOVR_W<'_>[src]
Bit 2 - Status Bit for Alarm Indicating Overvoltage for VREG
pub fn range1(&mut self) -> RANGE1_W<'_>[src]
Bit 8 - VBAT Range1 (> 2.75v)
pub fn range2(&mut self) -> RANGE2_W<'_>[src]
Bit 9 - VBAT Range2 (2.75v - 2.3v)
pub fn range3(&mut self) -> RANGE3_W<'_>[src]
Bit 10 - VBAT Range3 (2.3v - 1.6v)
impl W<u32, Reg<u32, _PWRMOD>>[src]
pub fn mode(&mut self) -> MODE_W<'_>[src]
Bits 0:1 - Power Mode Bits
pub fn monvbatn(&mut self) -> MONVBATN_W<'_>[src]
Bit 3 - Monitor VBAT During Hibernate Mode. Monitors VBAT by Default
impl W<u32, Reg<u32, _PWRKEY>>[src]
impl W<u32, Reg<u32, _SRAMRET>>[src]
pub fn bnk1en(&mut self) -> BNK1EN_W<'_>[src]
Bit 0 - Enable Retention Bank 1 (8kB)
pub fn bnk2en(&mut self) -> BNK2EN_W<'_>[src]
Bit 1 - Enable Retention Bank 2 (16kB)
impl W<u32, Reg<u32, _RST_STAT>>[src]
pub fn por(&mut self) -> POR_W<'_>[src]
Bit 0 - Power-on-Reset
pub fn extrst(&mut self) -> EXTRST_W<'_>[src]
Bit 1 - External Reset
pub fn wdrst(&mut self) -> WDRST_W<'_>[src]
Bit 2 - Watchdog Time-out Reset
pub fn swrst(&mut self) -> SWRST_W<'_>[src]
Bit 3 - Software Reset
impl W<u32, Reg<u32, _CTL1>>[src]
pub fn hpbucken(&mut self) -> HPBUCKEN_W<'_>[src]
Bit 0 - Enable HP Buck
impl W<u32, Reg<u32, _CFG0>>[src]
pub fn irq0mde(&mut self) -> IRQ0MDE_W<'_>[src]
Bits 0:2 - External Interrupt 0 Mode Registers
pub fn irq0en(&mut self) -> IRQ0EN_W<'_>[src]
Bit 3 - External Interrupt 0 Enable Bit
pub fn irq1mde(&mut self) -> IRQ1MDE_W<'_>[src]
Bits 4:6 - External Interrupt 1 Mode Registers
pub fn irq1en(&mut self) -> IRQ1EN_W<'_>[src]
Bit 7 - External Interrupt 1 Enable Bit
pub fn irq2mde(&mut self) -> IRQ2MDE_W<'_>[src]
Bits 8:10 - External Interrupt 2 Mode Registers
pub fn irq2en(&mut self) -> IRQ2EN_W<'_>[src]
Bit 11 - External Interrupt 2 Enable Bit
pub fn irq3mde(&mut self) -> IRQ3MDE_W<'_>[src]
Bits 12:14 - External Interrupt 3 Mode Registers
pub fn irq3en(&mut self) -> IRQ3EN_W<'_>[src]
Bit 15 - External Interrupt 3 Enable Bit
pub fn uart_rx_en(&mut self) -> UART_RX_EN_W<'_>[src]
Bit 20 - External Interrupt Enable Bit
pub fn uart_rx_mde(&mut self) -> UART_RX_MDE_W<'_>[src]
Bits 21:23 - External Interrupt Using UART_RX Wakeup Mode Registers
impl W<u32, Reg<u32, _CLR>>[src]
pub fn irq0(&mut self) -> IRQ0_W<'_>[src]
Bit 0 - External Interrupt 0
pub fn irq1(&mut self) -> IRQ1_W<'_>[src]
Bit 1 - External Interrupt 1
pub fn irq2(&mut self) -> IRQ2_W<'_>[src]
Bit 2 - External Interrupt 2
pub fn irq3(&mut self) -> IRQ3_W<'_>[src]
Bit 3 - External Interrupt 3
pub fn uart_rx_clr(&mut self) -> UART_RX_CLR_W<'_>[src]
Bit 5 - External Interrupt Clear for UART_RX Wakeup Interrupt
impl W<u32, Reg<u32, _NMICLR>>[src]
impl W<u32, Reg<u32, _KEY>>[src]
impl W<u32, Reg<u32, _CTL>>[src]
pub fn lfclkmux(&mut self) -> LFCLKMUX_W<'_>[src]
Bit 0 - 32kHz Clock Select Mux
pub fn hfoscen(&mut self) -> HFOSCEN_W<'_>[src]
Bit 1 - High Frequency Internal Oscillator Enable
pub fn lfxtalen(&mut self) -> LFXTALEN_W<'_>[src]
Bit 2 - Low Frequency Crystal Oscillator Enable
pub fn hfxtalen(&mut self) -> HFXTALEN_W<'_>[src]
Bit 3 - High Frequency Crystal Oscillator Enable
pub fn lfxtal_bypass(&mut self) -> LFXTAL_BYPASS_W<'_>[src]
Bit 4 - Low Frequency Crystal Oscillator Bypass
pub fn lfxtal_mon_en(&mut self) -> LFXTAL_MON_EN_W<'_>[src]
Bit 5 - LFXTAL Clock Monitor and Clock Fail Interrupt Enable
pub fn lfxtal_mon_fail_stat(&mut self) -> LFXTAL_MON_FAIL_STAT_W<'_>[src]
Bit 31 - LFXTAL Not Stable
impl W<u32, Reg<u32, _SRAM_CTL>>[src]
pub fn bnk0en(&mut self) -> BNK0EN_W<'_>[src]
Bit 0 - Enable Initialization of SRAM Bank 0
pub fn bnk1en(&mut self) -> BNK1EN_W<'_>[src]
Bit 1 - Enable Initialization of SRAM Bank 1
pub fn bnk2en(&mut self) -> BNK2EN_W<'_>[src]
Bit 2 - Enable Initialization of SRAM Bank 2
pub fn bnk3en(&mut self) -> BNK3EN_W<'_>[src]
Bit 3 - Enable Initialization of SRAM Bank 3
pub fn bnk4en(&mut self) -> BNK4EN_W<'_>[src]
Bit 4 - Enable Initialization of SRAM Bank 4
pub fn bnk5en(&mut self) -> BNK5EN_W<'_>[src]
Bit 5 - Enable Initialization of SRAM Bank 5
pub fn startinit(&mut self) -> STARTINIT_W<'_>[src]
Bit 13 - Write 1 to Trigger Initialization
pub fn autoinit(&mut self) -> AUTOINIT_W<'_>[src]
Bit 14 - Automatic Initialization on Wakeup from Hibernate Mode
pub fn abtinit(&mut self) -> ABTINIT_W<'_>[src]
Bit 15 - Abort Current Initialization. Self-cleared
pub fn penbnk0(&mut self) -> PENBNK0_W<'_>[src]
Bit 16 - Enable Parity Check SRAM Bank 0
pub fn penbnk1(&mut self) -> PENBNK1_W<'_>[src]
Bit 17 - Enable Parity Check SRAM Bank 1
pub fn penbnk2(&mut self) -> PENBNK2_W<'_>[src]
Bit 18 - Enable Parity Check SRAM Bank 2
pub fn penbnk3(&mut self) -> PENBNK3_W<'_>[src]
Bit 19 - Enable Parity Check SRAM Bank 3
pub fn penbnk4(&mut self) -> PENBNK4_W<'_>[src]
Bit 20 - Enable Parity Check SRAM Bank 4
pub fn penbnk5(&mut self) -> PENBNK5_W<'_>[src]
Bit 21 - Enable Parity Check SRAM Bank 5
pub fn instren(&mut self) -> INSTREN_W<'_>[src]
Bit 31 - Enables Instruction SRAM
impl W<u16, Reg<u16, _CLR_LATCH_GPIOS>>[src]
impl W<u32, Reg<u32, _SCRPAD_IMG>>[src]
impl W<u32, Reg<u32, _CTL0>>[src]
pub fn clkmux(&mut self) -> CLKMUX_W<'_>[src]
Bits 0:1 - Clock Mux Select
pub fn clkout(&mut self) -> CLKOUT_W<'_>[src]
Bits 3:6 - GPIO Clock Out Select (for Debug)
pub fn rclkmux(&mut self) -> RCLKMUX_W<'_>[src]
Bits 8:9 - Flash Reference Clock and HP Buck Source Mux
pub fn spllipsel(&mut self) -> SPLLIPSEL_W<'_>[src]
Bit 11 - SPLL Source Select Mux
pub fn lfxtalie(&mut self) -> LFXTALIE_W<'_>[src]
Bit 14 - Low Frequency Crystal Interrupt Enable
pub fn hfxtalie(&mut self) -> HFXTALIE_W<'_>[src]
Bit 15 - High Frequency Crystal Interrupt Enable
impl W<u32, Reg<u32, _CTL1>>[src]
pub fn hclkdivcnt(&mut self) -> HCLKDIVCNT_W<'_>[src]
Bits 0:5 - HCLK Divide Count
pub fn pclkdivcnt(&mut self) -> PCLKDIVCNT_W<'_>[src]
Bits 8:13 - PCLK Divide Count
pub fn aclkdivcnt(&mut self) -> ACLKDIVCNT_W<'_>[src]
Bits 16:23 - ACLK Divide Count
impl W<u32, Reg<u32, _CTL3>>[src]
pub fn spllnsel(&mut self) -> SPLLNSEL_W<'_>[src]
Bits 0:4 - System PLL N Multiplier
pub fn splldiv2(&mut self) -> SPLLDIV2_W<'_>[src]
Bit 8 - System PLL Division by 2
pub fn spllen(&mut self) -> SPLLEN_W<'_>[src]
Bit 9 - System PLL Enable
pub fn spllie(&mut self) -> SPLLIE_W<'_>[src]
Bit 10 - System PLL Interrupt Enable
pub fn spllmsel(&mut self) -> SPLLMSEL_W<'_>[src]
Bits 11:14 - System PLL M Divider
pub fn spllmul2(&mut self) -> SPLLMUL2_W<'_>[src]
Bit 16 - System PLL Multiply by 2
impl W<u32, Reg<u32, _CTL5>>[src]
pub fn gptclk0off(&mut self) -> GPTCLK0OFF_W<'_>[src]
Bit 0 - Timer 0 User Control
pub fn gptclk1off(&mut self) -> GPTCLK1OFF_W<'_>[src]
Bit 1 - Timer 1 User Control
pub fn gptclk2off(&mut self) -> GPTCLK2OFF_W<'_>[src]
Bit 2 - Timer 2 User Control
pub fn uclki2coff(&mut self) -> UCLKI2COFF_W<'_>[src]
Bit 3 - I2C Clock User Control
pub fn gpioclkoff(&mut self) -> GPIOCLKOFF_W<'_>[src]
Bit 4 - GPIO Clock Control
pub fn perclkoff(&mut self) -> PERCLKOFF_W<'_>[src]
Bit 5 - Disables All Clocks Connected to All Peripherals
impl W<u32, Reg<u32, _STAT0>>[src]
pub fn splllk(&mut self) -> SPLLLK_W<'_>[src]
Bit 1 - System PLL Lock
pub fn spllunlk(&mut self) -> SPLLUNLK_W<'_>[src]
Bit 2 - System PLL Unlock
pub fn lfxtalok(&mut self) -> LFXTALOK_W<'_>[src]
Bit 9 - LF Crystal Stable
pub fn lfxtalnok(&mut self) -> LFXTALNOK_W<'_>[src]
Bit 10 - LF Crystal Not Stable
pub fn hfxtalok(&mut self) -> HFXTALOK_W<'_>[src]
Bit 13 - HF Crystal Stable
pub fn hfxtalnok(&mut self) -> HFXTALNOK_W<'_>[src]
Bit 14 - HF Crystal Not Stable
impl W<u32, Reg<u32, _ARBIT0>>[src]
pub fn flsh_dcode(&mut self) -> FLSH_DCODE_W<'_>[src]
Bits 0:1 - Flash priority for DCODE
pub fn flsh_sbus(&mut self) -> FLSH_SBUS_W<'_>[src]
Bits 2:3 - Flash priority for SBUS
pub fn flsh_dma0(&mut self) -> FLSH_DMA0_W<'_>[src]
Bits 4:5 - Flash priority for DMA0
pub fn sram0_dcode(&mut self) -> SRAM0_DCODE_W<'_>[src]
Bits 16:17 - SRAM0 priority for Dcode
pub fn sram0_sbus(&mut self) -> SRAM0_SBUS_W<'_>[src]
Bits 18:19 - SRAM0 priority for SBUS
pub fn sram0_dma0(&mut self) -> SRAM0_DMA0_W<'_>[src]
Bits 20:21 - SRAM0 priority for DMA0
impl W<u32, Reg<u32, _ARBIT1>>[src]
pub fn sram1_dcode(&mut self) -> SRAM1_DCODE_W<'_>[src]
Bits 0:1 - SRAM1 priority for Dcode
pub fn sram1_sbus(&mut self) -> SRAM1_SBUS_W<'_>[src]
Bits 2:3 - SRAM1 priority for SBUS
pub fn sram1_dma0(&mut self) -> SRAM1_DMA0_W<'_>[src]
Bits 4:5 - SRAM1 priority for DMA0
pub fn sip_dcode(&mut self) -> SIP_DCODE_W<'_>[src]
Bits 16:17 - SIP priority for DCODE
pub fn sip_sbus(&mut self) -> SIP_SBUS_W<'_>[src]
Bits 18:19 - SIP priority for SBUS
pub fn sip_dma0(&mut self) -> SIP_DMA0_W<'_>[src]
Bits 20:21 - SIP priority for DMA0
impl W<u32, Reg<u32, _ARBIT2>>[src]
pub fn apb32_dcode(&mut self) -> APB32_DCODE_W<'_>[src]
Bits 0:1 - APB32 priority for DCODE
pub fn apb32_sbus(&mut self) -> APB32_SBUS_W<'_>[src]
Bits 2:3 - APB32 priority for SBUS
pub fn apb32_dma0(&mut self) -> APB32_DMA0_W<'_>[src]
Bits 4:5 - APB32 priority for DMA0
pub fn apb16_dcode(&mut self) -> APB16_DCODE_W<'_>[src]
Bits 16:17 - APB16 priority for DCODE
pub fn apb16_sbus(&mut self) -> APB16_SBUS_W<'_>[src]
Bits 18:19 - APB16 priority for SBUS
pub fn apb16_dma0(&mut self) -> APB16_DMA0_W<'_>[src]
Bits 20:21 - APB16 priority for DMA0
impl W<u32, Reg<u32, _ARBIT3>>[src]
pub fn apb16_core(&mut self) -> APB16_CORE_W<'_>[src]
Bit 0 - APB16 priority for CORE
pub fn apb16_dma1(&mut self) -> APB16_DMA1_W<'_>[src]
Bit 1 - APB16 priority for DMA1
pub fn apb16_4dma_core(&mut self) -> APB16_4DMA_CORE_W<'_>[src]
Bit 16 - APB16 for dma priority for CORE
pub fn apb16_4dma_dma1(&mut self) -> APB16_4DMA_DMA1_W<'_>[src]
Bit 17 - APB16 for dma priority for DMA1
impl W<u32, Reg<u32, _INTNUM>>[src]
impl W<u32, Reg<u32, _STKSTA>>[src]
impl W<u32, Reg<u32, _STKLD>>[src]
impl W<u32, Reg<u32, _STKVAL>>[src]
impl W<u32, Reg<u32, _STKCAL>>[src]
impl W<u32, Reg<u32, _INTSETE0>>[src]
impl W<u32, Reg<u32, _INTSETE1>>[src]
impl W<u32, Reg<u32, _INTCLRE0>>[src]
impl W<u32, Reg<u32, _INTCLRE1>>[src]
impl W<u32, Reg<u32, _INTSETP0>>[src]
impl W<u32, Reg<u32, _INTSETP1>>[src]
impl W<u32, Reg<u32, _INTCLRP0>>[src]
impl W<u32, Reg<u32, _INTCLRP1>>[src]
impl W<u32, Reg<u32, _INTACT0>>[src]
impl W<u32, Reg<u32, _INTACT1>>[src]
impl W<u32, Reg<u32, _INTPRI0>>[src]
impl W<u32, Reg<u32, _INTPRI1>>[src]
impl W<u32, Reg<u32, _INTPRI2>>[src]
impl W<u32, Reg<u32, _INTPRI3>>[src]
impl W<u32, Reg<u32, _INTPRI4>>[src]
impl W<u32, Reg<u32, _INTPRI5>>[src]
impl W<u32, Reg<u32, _INTPRI6>>[src]
impl W<u32, Reg<u32, _INTPRI7>>[src]
impl W<u32, Reg<u32, _INTPRI8>>[src]
impl W<u32, Reg<u32, _INTPRI9>>[src]
impl W<u32, Reg<u32, _INTPRI10>>[src]
impl W<u32, Reg<u32, _INTCPID>>[src]
impl W<u32, Reg<u32, _INTSTA>>[src]
impl W<u32, Reg<u32, _INTVEC>>[src]
impl W<u32, Reg<u32, _INTAIRC>>[src]
impl W<u16, Reg<u16, _INTCON0>>[src]
pub fn sleeponexit(&mut self) -> SLEEPONEXIT_W<'_>[src]
Bit 1 - Sleeps the core on exit from an ISR
pub fn sleepdeep(&mut self) -> SLEEPDEEP_W<'_>[src]
Bit 2 - deep sleep flag for HIBERNATE mode
impl W<u32, Reg<u32, _INTCON1>>[src]
impl W<u32, Reg<u32, _INTSHPRIO0>>[src]
impl W<u32, Reg<u32, _INTSHPRIO1>>[src]
impl W<u32, Reg<u32, _INTSHPRIO3>>[src]
impl W<u32, Reg<u32, _INTSHCSR>>[src]
impl W<u32, Reg<u32, _INTCFSR>>[src]
impl W<u32, Reg<u32, _INTHFSR>>[src]
impl W<u32, Reg<u32, _INTDFSR>>[src]
impl W<u32, Reg<u32, _INTMMAR>>[src]
impl W<u32, Reg<u32, _INTBFAR>>[src]
impl W<u32, Reg<u32, _INTAFSR>>[src]
impl W<u32, Reg<u32, _INTPFR0>>[src]
impl W<u32, Reg<u32, _INTPFR1>>[src]
impl W<u32, Reg<u32, _INTDFR0>>[src]
impl W<u32, Reg<u32, _INTAFR0>>[src]
impl W<u32, Reg<u32, _INTMMFR0>>[src]
impl W<u32, Reg<u32, _INTMMFR1>>[src]
impl W<u32, Reg<u32, _INTMMFR2>>[src]
impl W<u32, Reg<u32, _INTMMFR3>>[src]
impl W<u32, Reg<u32, _INTISAR0>>[src]
impl W<u32, Reg<u32, _INTISAR1>>[src]
impl W<u32, Reg<u32, _INTISAR2>>[src]
impl W<u32, Reg<u32, _INTISAR3>>[src]
impl W<u32, Reg<u32, _INTISAR4>>[src]
impl W<u32, Reg<u32, _INTTRGI>>[src]
impl W<u32, Reg<u32, _INTPID4>>[src]
impl W<u32, Reg<u32, _INTPID5>>[src]
impl W<u32, Reg<u32, _INTPID6>>[src]
impl W<u32, Reg<u32, _INTPID7>>[src]
impl W<u32, Reg<u32, _INTPID0>>[src]
impl W<u32, Reg<u32, _INTPID1>>[src]
impl W<u32, Reg<u32, _INTPID2>>[src]
impl W<u32, Reg<u32, _INTPID3>>[src]
impl W<u32, Reg<u32, _INTCID0>>[src]
impl W<u32, Reg<u32, _INTCID1>>[src]
impl W<u32, Reg<u32, _INTCID2>>[src]
impl W<u32, Reg<u32, _INTCID3>>[src]
Auto Trait Implementations
impl<U, REG> Send for W<U, REG> where
REG: Send,
U: Send, [src]
REG: Send,
U: Send,
impl<U, REG> Sync for W<U, REG> where
REG: Sync,
U: Sync, [src]
REG: Sync,
U: Sync,
impl<U, REG> Unpin for W<U, REG> where
REG: Unpin,
U: Unpin, [src]
REG: Unpin,
U: Unpin,
Blanket Implementations
impl<T> Any for T where
T: 'static + ?Sized, [src]
T: 'static + ?Sized,
impl<T> Borrow<T> for T where
T: ?Sized, [src]
T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized, [src]
T: ?Sized,
pub fn borrow_mut(&mut self) -> &mut T[src]
impl<T> From<T> for T[src]
impl<T, U> Into<U> for T where
U: From<T>, [src]
U: From<T>,
impl<T> Same<T> for T
type Output = T
Should always be Self
impl<T, U> TryFrom<U> for T where
U: Into<T>, [src]
U: Into<T>,
type Error = Infallible
The type returned in the event of a conversion error.
pub fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>[src]
impl<T, U> TryInto<U> for T where
U: TryFrom<T>, [src]
U: TryFrom<T>,