[−][src]Struct ADuCM302x::adc0::RegisterBlock

#[repr(C)]pub struct RegisterBlock {
    pub cfg: CFG,
    pub pwrup: PWRUP,
    pub cal_word: CAL_WORD,
    pub cnv_cfg: CNV_CFG,
    pub cnv_time: CNV_TIME,
    pub avg_cfg: AVG_CFG,
    pub irq_en: IRQ_EN,
    pub stat: STAT,
    pub ovf: OVF,
    pub alert: ALERT,
    pub ch0_out: CH0_OUT,
    pub ch1_out: CH1_OUT,
    pub ch2_out: CH2_OUT,
    pub ch3_out: CH3_OUT,
    pub ch4_out: CH4_OUT,
    pub ch5_out: CH5_OUT,
    pub ch6_out: CH6_OUT,
    pub ch7_out: CH7_OUT,
    pub bat_out: BAT_OUT,
    pub tmp_out: TMP_OUT,
    pub tmp2_out: TMP2_OUT,
    pub dma_out: DMA_OUT,
    pub lim0_lo: LIM0_LO,
    pub lim0_hi: LIM0_HI,
    pub hys0: HYS0,
    pub lim1_lo: LIM1_LO,
    pub lim1_hi: LIM1_HI,
    pub hys1: HYS1,
    pub lim2_lo: LIM2_LO,
    pub lim2_hi: LIM2_HI,
    pub hys2: HYS2,
    pub lim3_lo: LIM3_LO,
    pub lim3_hi: LIM3_HI,
    pub hys3: HYS3,
    pub cfg1: CFG1,
    // some fields omitted
}

Register block

Fields

cfg: CFG

0x00 - ADC Configuration

pwrup: PWRUP

0x04 - ADC Power-up Time

cal_word: CAL_WORD

0x08 - Calibration Word

cnv_cfg: CNV_CFG

0x0c - ADC Conversion Configuration

cnv_time: CNV_TIME

0x10 - ADC Conversion Time

avg_cfg: AVG_CFG

0x14 - Averaging Configuration

irq_en: IRQ_EN

0x20 - Interrupt Enable

stat: STAT

0x24 - ADC Status

ovf: OVF

0x28 - Overflow of Output Registers

alert: ALERT

0x2c - Alert Indication

ch0_out: CH0_OUT

0x30 - Conversion Result Channel 0

ch1_out: CH1_OUT

0x34 - Conversion Result Channel 1

ch2_out: CH2_OUT

0x38 - Conversion Result Channel 2

ch3_out: CH3_OUT

0x3c - Conversion Result Channel 3

ch4_out: CH4_OUT

0x40 - Conversion Result Channel 4

ch5_out: CH5_OUT

0x44 - Conversion Result Channel 5

ch6_out: CH6_OUT

0x48 - Conversion Result Channel 6

ch7_out: CH7_OUT

0x4c - Conversion Result Channel 7

bat_out: BAT_OUT

0x50 - Battery Monitoring Result

tmp_out: TMP_OUT

0x54 - Temperature Result

tmp2_out: TMP2_OUT

0x58 - Temperature Result 2

dma_out: DMA_OUT

0x5c - DMA Output Register

lim0_lo: LIM0_LO

0x60 - Channel 0 Low Limit

lim0_hi: LIM0_HI

0x64 - Channel 0 High Limit

hys0: HYS0

0x68 - Channel 0 Hysteresis

lim1_lo: LIM1_LO

0x70 - Channel 1 Low Limit

lim1_hi: LIM1_HI

0x74 - Channel 1 High Limit

hys1: HYS1

0x78 - Channel 1 Hysteresis

lim2_lo: LIM2_LO

0x80 - Channel 2 Low Limit

lim2_hi: LIM2_HI

0x84 - Channel 2 High Limit

hys2: HYS2

0x88 - Channel 2 Hysteresis

lim3_lo: LIM3_LO

0x90 - Channel 3 Low Limit

lim3_hi: LIM3_HI

0x94 - Channel 3 High Limit

hys3: HYS3

0x98 - Channel 3 Hysteresis

cfg1: CFG1

0xc0 - Reference Buffer Low Power Mode

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