Docs.rs

Test and conformance harness of the vj SystemVerilog simulator.

Netlist, scheduler and process model of the vj SystemVerilog simulator.

The single source of the Rós Madair extension-type registry: handler declarations shared by emitter and query side (WASM-buildable)

SDF (IEEE 1497) back-annotation for the vj SystemVerilog simulator.

Kernel ABI shared by the vj SystemVerilog simulator's compiler and runtime.

Bytecode interpreter and compiler contracts for Harn execution backends

Code formatter for the Harn programming language

Durable Harn session event store primitives

Shared provider catalog, capability policy, model metadata, and presentation contracts.

Cross-process SQLite initialization primitives for Harn runtimes

Portable compiler, program artifact, and deterministic execution kernel for Harn

Conformance runner for the CortexKit llm-runner/v1 role: drives a live runner through its crash-cut harness with a scripted model and checks its wire replies.

Cross-file module graph and import resolution utilities for Harn

Shared Harn prompt-template syntax, vocabulary, lint analysis, and outlines.

CFG and invariant analysis for the Harn programming language