Struct rk3399_pac::PcieCore

pub struct PcieCore { /* private fields */ }

PCIe Core Registers

Implementations

impl PcieCore

pub const PTR: *const RegisterBlock = {0xfd800000 as *const pcie_core::RegisterBlock}

Pointer to the register block

pub const fn ptr() -> *const RegisterBlock

Return the pointer to the register block

pub unsafe fn steal() -> Self

Steal an instance of this peripheral

Safety

Ensure that the new instance of the peripheral cannot be used in a way that may race with any existing instances, for example by only accessing read-only or write-only registers, or by consuming the original peripheral and using critical sections to coordinate access between multiple new instances.

Additionally, other software such as HALs may rely on only one peripheral instance existing to ensure memory safety; ensure no stolen instances are passed to such software.

Methods from Deref<Target = RegisterBlock>

pub fn pcie_pf_vendor_id_and_device_id(&self) -> &PciePfVendorIdAndDeviceId

0x00 - Vendor ID and Device ID

Device ID assigned by the

manufacturer of the device. On

power-up, the core sets it to the

value defined in the RTL file

reg_defaults.h. This field can be

rewritten independently for each

Function from the local management

bus.

pub fn pcie_pf_command_and_status(&self) -> &PciePfCommandAndStatus

0x04 - Command and Status Register

This bit is set when the core has

received a poisoned TLP. The Parity

Error Response enable bit (bit 6) has

no effect on the setting of this bit.

This field can also be cleared from

the local management bus by writing

a 1 into this bit position.

pub fn pcie_pf_revision_id_and_class_code( &self ) -> &PciePfRevisionIdAndClassCode

0x08 - Revision ID and Class Code Register

Identifies the function of the device.

On power- up, the core sets it to

the value defined in the RTL file

reg_defaults.h. This field can be

rewritten independently for each

Function from the local management

bus

pub fn pcie_pf_bist_header_type_latency_timer_and_cache_line_size_s( &self ) -> &PciePfBistHeaderTypeLatencyTimerAndCacheLineSizeS

0x0c - BIST, Header Type, Latency Timer and Cache Line Size Registers

BIST control register.It can be

accessed using local management

bus.

pub fn pcie_pf_base_address_0(&self) -> &PciePfBaseAddress0

0x10 - Base Address Register 0

This field defines the base address

of the memory address range. The

number of implemented bits in this

field determines the BAR aperture

configured in BAR Configuration

Registers of the associated Physical

Function.

pub fn pcie_pf_base_address_1(&self) -> &PciePfBaseAddress1

0x14 - Base Address Register 1

This field defines the base address of

the memory address range. The

number of implemented bits in this

field determines the BAR aperture

setting of BAR Configuration

Registers of the associated

Physical Function. All other bits are

not writeable, and are read as 0’s.

pub fn pcie_pf_base_address_2(&self) -> &PciePfBaseAddress2

0x18 - Base Address Register 2

This field defines the base address

of the memory address range. The

number of implemented bits in this

field determines the BAR aperture

configured in BAR Configuration

Registers of the associated Physical

Function.

pub fn pcie_pf_base_address_3(&self) -> &PciePfBaseAddress3

0x1c - Base Address Register 3

This field defines the base address of

the memory address range. The

number of implemented bits in this

field determines the BAR aperture

setting of BAR Configuration

Registers of the associated

Physical Function. All other bits are

not writeable, and are read as 0’s.

pub fn pcie_pf_base_address_4(&self) -> &PciePfBaseAddress4

0x20 - Base Address Register 4

This field defines the base address

of the memory address range. The

number of implemented bits in this

field determines the BAR aperture

configured in BAR Configuration

Registers of the associated Physical

Function.

pub fn pcie_pf_base_address_5(&self) -> &PciePfBaseAddress5

0x24 - Base Address Register 5

This field defines the base address of

the memory address range. The

number of implemented bits in this

field determines the BAR aperture

setting of BAR Configuration

Registers of the associated Physical

Function. All other bits are not

writeable, and are read as 0’s.

pub fn pcie_pf_subsystem_vendor_id_and_subsystem_id( &self ) -> &PciePfSubsystemVendorIdAndSubsystemId

0x2c - Subsystem Vendor ID and Subsystem ID Register

Specifies the Subsystem ID assigned

by the manufacturer of the device.

On power-up, the core sets it to the

value defined in the RTL file

reg_defaults.h. This field can be re-

written independently for each

Function from the local management

bus.

pub fn pcie_pf_capabilities_pointer(&self) -> &PciePfCapabilitiesPointer

0x34 - Capabilities Pointer

Reserved

pub fn pcie_pf_interrupt_line_and_interrupt_pin( &self ) -> &PciePfInterruptLineAndInterruptPin

0x3c - Interrupt Line and Interrupt Pin Register

Reserved

pub fn pcie_pf_power_management_capabilities( &self ) -> &PciePfPowerManagementCapabilities

0x80 - Power Management Capabilities Register

Indicates whether the Function is

capable of sending PME messages

when in the D3cold state. Because

the device does not have aux power,

this bit is hardwired to 0.

pub fn pcie_pf_power_management_control_status_report( &self ) -> &PciePfPowerManagementControlStatusReport

0x84 - Power Management Control/Status Report

This optional register is not

implemented in the PCIe core. This

field is hardwired to 0.

pub fn pcie_pf_msi_control(&self) -> &PciePfMsiControl

0x90 - MSI Control Register

Reserved

pub fn pcie_pf_msi_message_low_address(&self) -> &PciePfMsiMessageLowAddress

0x94 - MSI Message Low Address Register

Lower bits of the address to be used

in MSI messages. This field can also

be written from the local

management bus.

pub fn pcie_pf_msi_message_high_address(&self) -> &PciePfMsiMessageHighAddress

0x98 - MSI Message High Address Register

Contains bits 63:32 of the 64-bit

address to be used in MSI Messages.

A value of 0 specifies that 32-bit

addresses are to be used in the

messages. This field can also be

written from the local management

bus.

pub fn pcie_pf_msi_message_data(&self) -> &PciePfMsiMessageData

0x9c - MSI Message Data Register

Hardwired to 0

pub fn pcie_pf_msi_mask(&self) -> &PciePfMsiMask

0xa0 - MSI Mask Register

Please note that if the Multiple

Message Capable field is changed

from the local management APB bus,

then the width of this field also

changes correspondingly

pub fn pcie_pf_msi_pending_bits(&self) -> &PciePfMsiPendingBits

0xa4 - MSI Pending Bits Register

Please note that if the Multiple

Message Capable field is changed

from the local management APB bus,

then the width of this field also

changes correspondingly

pub fn pcie_pf_msi_x_control(&self) -> &PciePfMsiXControl

0xb0 - MSI-X Control Register

Set by the configuration program to

enable the MSI-X feature. This field

can also be written from the local

management bus.

pub fn pcie_pf_msi_x_table_offset(&self) -> &PciePfMsiXTableOffset

0xb4 - MSI-X Table Offset Register

Offset of the memory address where

the MSI- X Table is located, relative

to the selected BAR. The three least

significant bits of the address are

omitted, as the addresses are

QWORD aligned.

pub fn pcie_pf_msi_x_pending_interrupt(&self) -> &PciePfMsiXPendingInterrupt

0xb8 - MSI-X Pending Interrupt Register

Offset of the memory address where

the PBA is located, relative to the

selected BAR. The three least

significant bits of the address are

omitted, as the addresses are

QWORD aligned.

pub fn pcie_pf_pci_express_capability_list( &self ) -> &PciePfPciExpressCapabilityList

0xc0 - PCI Express Capability List Register

Reserved

pub fn pcie_pf_pci_express_device_capabilities( &self ) -> &PciePfPciExpressDeviceCapabilities

0xc4 - PCI Express Device Capabilities Register

Reserved

pub fn pcie_pf_pci_express_device_control_and_status( &self ) -> &PciePfPciExpressDeviceControlAndStatus

0xc8 - PCI Express Device Control and Status Register

Reserved

pub fn pcie_pf_link_capabilities(&self) -> &PciePfLinkCapabilities

0xcc - Link Capabilities Register

Specifies the port number assigned

to the PCI Express link connected to

this device.

pub fn pcie_pf_link_control_and_status(&self) -> &PciePfLinkControlAndStatus

0xd0 - Link Control and Status Register

This bit is Set by hardware to

indicate that hardware has

autonomously changed Link speed

or width, without the Port

transitioning through DL_Down

status, for reasons other than to

attempt to correct unreliable Link

operation. This triggers an interrupt

to be generated through

PHY_INTERRUPT_OUT if enabled.

Hardwired to 0 if Link Bandwidth

Notification Capability is 0. Not

applicable to Endpoints where field

is hardwired to 0.

pub fn pcie_pf_pci_express_device_capabilities_2( &self ) -> &PciePfPciExpressDeviceCapabilities2

0xe4 - PCI Express Device Capabilities Register 2

Reserved

pub fn pcie_pf_pci_express_device_control_and_status_2( &self ) -> &PciePfPciExpressDeviceControlAndStatus2

0xe8 - PCI Express Device Control and Status Register 2

Reserved

pub fn pcie_pf_link_capabilities_2(&self) -> &PciePfLinkCapabilities2

0xec - Link Capabilities Register 2

RSVD

pub fn pcie_pf_link_control_and_status_2(&self) -> &PciePfLinkControlAndStatus2

0xf0 - Link Control and Status Register 2

Reserved

pub fn pcie_pf_advanced_error_reporting_aer_enhanced_capability_header( &self ) -> &PciePfAdvancedErrorReportingAerEnhancedCapabilityHeader

0x100 - Advanced Error Reporting (AER) Enhanced Capability Header Register

Indicates offset to the next PCI

Express capability structure. The

default next pointer value is dynamic

and is dependent on whether the

strap or LMI bits are set.

pub fn pcie_pf_uncorrectable_error_status( &self ) -> &PciePfUncorrectableErrorStatus

0x104 - Uncorrectable Error Status Register

(no description)

pub fn pcie_pf_uncorrectable_error_mask(&self) -> &PciePfUncorrectableErrorMask

0x108 - Uncorrectable Error Mask Register

Reserved

pub fn pcie_pf_uncorrectable_error_severity( &self ) -> &PciePfUncorrectableErrorSeverity

0x10c - Uncorrectable Error Severity Register

Reserved

pub fn pcie_pf_correctable_error_status(&self) -> &PciePfCorrectableErrorStatus

0x110 - Correctable Error Status Register

Reserved

pub fn pcie_pf_correctable_error_mask(&self) -> &PciePfCorrectableErrorMask

0x114 - Correctable Error Mask Register

Reserved

pub fn pcie_pf_advanced_error_capabilities_and_control( &self ) -> &PciePfAdvancedErrorCapabilitiesAndControl

0x118 - Advanced Error Capabilities and Control Register

Reserved

pub fn pcie_pf_header_log_0(&self) -> &PciePfHeaderLog0

0x11c - Header Log Register 0

First DWORD of captured TLP header

STICKY.

pub fn pcie_pf_header_log_1(&self) -> &PciePfHeaderLog1

0x120 - Header Log Register 1

Second DWORD of captured TLP

header STICKY.

pub fn pcie_pf_header_log_2(&self) -> &PciePfHeaderLog2

0x124 - Header Log Register 2

Third DWORD of captured TLP

header STICKY.

pub fn pcie_pf_header_log_3(&self) -> &PciePfHeaderLog3

0x128 - Header Log Register 3

Fourth DWORD of captured TLP

header STICKY.

pub fn pcie_pf_ari_extended_capability_header( &self ) -> &PciePfAriExtendedCapabilityHeader

0x140 - ARI Extended Capability Header Register

Indicates offset to the next PCI

Express capability structure. The

default next pointer value is dynamic

and is dependent on whether the

strap or LMI bits are set.

pub fn pcie_pf_ari_capability_and_ari_control( &self ) -> &PciePfAriCapabilityAndAriControl

0x144 - ARI Capability Register and ARI Control Register

ARI Control Register not

implemented in this core. This field

is hardwired to 0.

pub fn pcie_pf_power_budgeting_enhanced_capability_header( &self ) -> &PciePfPowerBudgetingEnhancedCapabilityHeader

0x160 - Power Budgeting Enhanced Capability Header

Indicates offset to the next PCI

Express capability structure. The

default next pointer value is dynamic

and is dependent on whether the

strap or LMI bits are set.

pub fn pcie_pf_power_budgeting_data_select( &self ) -> &PciePfPowerBudgetingDataSelect

0x164 - Power Budgeting Data Select Register

(no description)

pub fn pcie_pf_power_budgeting_data(&self) -> &PciePfPowerBudgetingData

0x168 - Power Budgeting Data Register

Reserved

pub fn pcie_pf_power_budget_capability(&self) -> &PciePfPowerBudgetCapability

0x16c - Power Budget Capability Register

Reserved

pub fn pcie_pf_resizable_bar_extended_capability_header( &self ) -> &PciePfResizableBarExtendedCapabilityHeader

0x180 - Resizable BAR Extended Capability Header Register

Indicates offset to the next PCI

Express capability structure. The

default next pointer value is dynamic

and is dependent on whether the

strap or LMI bits are set.

pub fn pcie_pf_resizable_bar_capability_0( &self ) -> &PciePfResizableBarCapability0

0x184 - Resizable BAR Capability Register 0

Reserved

pub fn pcie_pf_resizable_bar_control_0(&self) -> &PciePfResizableBarControl0

0x188 - Resizable BAR Control Register 0

Reserved

pub fn pcie_pf_resizable_bar_capability_1( &self ) -> &PciePfResizableBarCapability1

0x18c - Resizable BAR Capability Register 1

Reserved

pub fn pcie_pf_resizable_bar_control_1(&self) -> &PciePfResizableBarControl1

0x190 - Resizable BAR Control Register 1

Reserved

pub fn pcie_pf_resizable_bar_capability_2( &self ) -> &PciePfResizableBarCapability2

0x194 - Resizable BAR Capability Register 2

Reserved

pub fn pcie_pf_resizable_bar_control_2(&self) -> &PciePfResizableBarControl2

0x198 - Resizable BAR Control Register 2

Reserved

pub fn pcie_pf_resizable_bar_capability_3( &self ) -> &PciePfResizableBarCapability3

0x19c - Resizable BAR Capability Register 3

Reserved

pub fn pcie_pf_resizable_bar_control_3(&self) -> &PciePfResizableBarControl3

0x1a0 - Resizable BAR Control Register 3

Reserved

pub fn pcie_pf_resizable_bar_capability_4( &self ) -> &PciePfResizableBarCapability4

0x1a4 - Resizable BAR Capability Register 4

Reserved

pub fn pcie_pf_resizable_bar_control_4(&self) -> &PciePfResizableBarControl4

0x1a8 - Resizable BAR Control Register 4

Reserved

pub fn pcie_pf_resizable_bar_capability_5( &self ) -> &PciePfResizableBarCapability5

0x1ac - Resizable BAR Capability Register 5

Reserved

pub fn pcie_pf_resizable_bar_control_5(&self) -> &PciePfResizableBarControl5

0x1b0 - Resizable BAR Control Register 5

Reserved

pub fn pcie_pf_latency_tolerance_reporting_ltr_extended_capability_header( &self ) -> &PciePfLatencyToleranceReportingLtrExtendedCapabilityHeader

0x1b8 - Latency Tolerance Reporting (LTR) Extended Capability Header Register

Indicates offset to the next PCI

Express capability structure. The

default next pointer value is dynamic

and is dependent on whether the

strap or LMI bits are set.

pub fn pcie_pf_ltr_max_snoop_max_no_snoop_latency( &self ) -> &PciePfLtrMaxSnoopMaxNoSnoopLatency

0x1bc - LTR Max Snoop/Max No-Snoop Latency Register

Reserved

pub fn pcie_pf_dpa_extended_capability_header( &self ) -> &PciePfDpaExtendedCapabilityHeader

0x1c0 - DPA Extended Capability Header Register

Indicates offset to the next PCI

Express capability structure. The

default next pointer value is dynamic

and is dependent on whether the

strap or LMI bits are set.

pub fn pcie_pf_dpa_capability(&self) -> &PciePfDpaCapability

0x1c4 - DPA Capability Register

Specifies the second of the two

transition latency values for the

substates. The unit of latency is

specified by the Transition Latency

Unit field of this register.

pub fn pcie_pf_dpa_latency_indicator(&self) -> &PciePfDpaLatencyIndicator

0x1c8 - DPA Latency Indicator Register

Bit i of this register indicates the

choice of the transition latency value

for substate i. A setting of 0

indicates that Transition Latency

Value 0 from the DPA Capability

Register applies to this substate; a

setting of 1 indicates that Transition

Latency Value 1 applies.

pub fn pcie_pf_dpa_control_and_status_s(&self) -> &PciePfDpaControlAndStatusS

0x1cc - DPA Control and Status Registers

Reserved

pub fn pcie_pf_dynamic_power_allocation_array_0( &self ) -> &PciePfDynamicPowerAllocationArray0

0x1d0 - Dynamic Power Allocation Array Register 0

This field contains the power

allocation for the DPA substate #3

covered by this register. This value,

when multiplied by the Power

Allocation Scale programmed in the

DPA Capability Register, provides the

power associated with the

corresponding substate in Watts.

pub fn pcie_pf_dynamic_power_allocation_array_1( &self ) -> &PciePfDynamicPowerAllocationArray1

0x1d4 - Dynamic Power Allocation Array Register 1

This field contains the power

allocation for the DPA substate #7

covered by this register. This value,

when multiplied by the Power

Allocation Scale programmed in the

DPA Capability Register, provides the

power associated with the

corresponding substate in Watts.

pub fn pcie_pf_sr_iov_extended_capability_header( &self ) -> &PciePfSrIovExtendedCapabilityHeader

0x200 - SR-IOV Extended Capability Header Register

Indicates offset to the next PCI

Express capability structure. The

default next pointer value is dynamic

and is dependent on whether the

strap or LMI bits are set.

pub fn pcie_pf_sr_iov_capabilities(&self) -> &PciePfSrIovCapabilities

0x204 - SR-IOV Capabilities Register

Reserved

pub fn pcie_pf_sr_iov_control_and_status_s( &self ) -> &PciePfSrIovControlAndStatusS

0x208 - SR-IOV Control and Status Registers

Not implemented.

pub fn pcie_pf_initial_vfs_total_vfs(&self) -> &PciePfInitialVfsTotalVfs

0x20c - Initial VFs/Total VFs Register

This field contains the total number

of VFs per PF. Its default setting is

identical to that of InitialVFs. This

field can be modified using local

management registers.

pub fn pcie_pf_function_dependency_link_numvfs( &self ) -> &PciePfFunctionDependencyLinkNumvfs

0x210 - Function Dependency Link/NumVFs Register

This field is used to specify

dependencies between PFs. It can be

modified independently for each

Function from the local management

bus.

pub fn pcie_pf_vf_offset_stride(&self) -> &PciePfVfOffsetStride

0x214 - VF Offset/Stride Register

Stride value used to assign RIDs for

VFs. The stride value is hardwired to

1 for all Physical Functions.

pub fn pcie_pf_vf_device_id(&self) -> &PciePfVfDeviceId

0x218 - VF Device ID Register

VF device id assigned to the device.

Its default value is specified in

reg_defaults.h, but can be re-

written independently for each PF

from the local management bus.

pub fn pcie_pf_supported_page_sizes(&self) -> &PciePfSupportedPageSizes

0x21c - Supported Page Sizes Register

Reserved

pub fn pcie_pf_system_page_size(&self) -> &PciePfSystemPageSize

0x220 - System Page Size Register

Reserved

pub fn pcie_pf_vf_base_address_0(&self) -> &PciePfVfBaseAddress0

0x224 - VF Base Address Register 0

This field defines the base address

of the memory address range. The

number of implemented bits in this

field determines the BAR aperture

configured in BAR Configuration

Registers of the associated Physical

Function.

pub fn pcie_pf_vf_base_address_1(&self) -> &PciePfVfBaseAddress1

0x228 - VF Base Address Register 1

This field defines the base address of

the memory address range. The

number of implemented bits in this

field determines the BAR aperture

setting of BAR Configuration

Registers of the associated Physical

Function. All other bits are not

writeable, and are read as 0’s.

pub fn pcie_pf_vf_base_address_2(&self) -> &PciePfVfBaseAddress2

0x22c - VF Base Address Register 2

This field defines the base address

of the memory address range. The

number of implemented bits in this

field determines the BAR aperture

configured in BAR Configuration

Registers of the associated Physical

Function.

pub fn pcie_pf_vf_base_address_3(&self) -> &PciePfVfBaseAddress3

0x230 - VF Base Address Register 3

This field defines the base address of

the memory address range. The

number of implemented bits in this

field determines the BAR aperture

setting of BAR Configuration

Registers of the associated Physical

Function. All other bits are not

writeable, and are read as 0’s.

pub fn pcie_pf_vf_base_address_4(&self) -> &PciePfVfBaseAddress4

0x234 - VF Base Address Register 4

This field defines the base address

of the memory address range. The

number of implemented bits in this

field determines the BAR aperture

configured in BAR Configuration

Registers of the associated Physical

Function.

pub fn pcie_pf_vf_base_address_5(&self) -> &PciePfVfBaseAddress5

0x238 - VF Base Address Register 5

This field defines the base address of

the memory address range. The

number of implemented bits in this

field determines the BAR aperture

setting of BAR Configuration

Registers of the associated Physical

Function. All other bits are not

writeable, and are read as 0’s.

pub fn pcie_pf_vf_migration_state_array_offset( &self ) -> &PciePfVfMigrationStateArrayOffset

0x23c - VF Migration State Array Offset Register

(no description)

pub fn pcie_pf_tph_requester_extended_capability_header( &self ) -> &PciePfTphRequesterExtendedCapabilityHeader

0x274 - TPH Requester Extended Capability Header Register

Indicates offset to the next PCI

Express capability structure. The

default next pointer value is dynamic

and is dependent on whether the

strap or LMI bits are set.

pub fn pcie_pf_tph_requester_capability(&self) -> &PciePfTphRequesterCapability

0x278 - TPH Requester Capability Register

Reserved

pub fn pcie_pf_tph_requester_control(&self) -> &PciePfTphRequesterControl

0x27c - TPH Requester Control Register

Reserved

pub fn pcie_pf_tph_st_table_0(&self) -> &PciePfTphStTable0

0x280 - TPH ST Table 0

This field is used for the upper 8 bits

of the second Steering Tag when

Extended TPH Requester support is

enabled.

pub fn pcie_pf_tph_st_table_1(&self) -> &PciePfTphStTable1

0x284 - TPH ST Table 1

This field is used for the upper 8 bits

of the second Steering Tag when

Extended TPH Requester support is

enabled.

pub fn pcie_pf_tph_st_table_2(&self) -> &PciePfTphStTable2

0x288 - TPH ST Table 2

This field is used for the upper 8 bits

of the second Steering Tag when

Extended TPH Requester support is

enabled.

pub fn pcie_pf_tph_st_table_3(&self) -> &PciePfTphStTable3

0x28c - TPH ST Table 3

This field is used for the upper 8 bits

of the second Steering Tag when

Extended TPH Requester support is

enabled.

pub fn pcie_pf_l1_pm_substates_extended_capability_header( &self ) -> &PciePfL1PmSubstatesExtendedCapabilityHeader

0x900 - L1 PM Substates Extended Capability Header Register

Indicates offset to the next PCI

Express capability structure. The

default next pointer value is dynamic

and is dependent on whether the

strap or LMI bits are set.

pub fn pcie_pf_l1_pm_substates_capabilities( &self ) -> &PciePfL1PmSubstatesCapabilities

0x904 - L1 PM Substates Capabilities Register

RSVD

pub fn pcie_pf_l1_pm_substates_control_1(&self) -> &PciePfL1PmSubstatesControl1

0x908 - L1 PM Substates Control 1 Register

(no description)

pub fn pcie_pf_l1_pm_substates_control_2(&self) -> &PciePfL1PmSubstatesControl2

0x90c - L1 PM Substates Control 2 Register

RSVD

pub fn pcie_vf_vendor_id_and_device_id(&self) -> &PcieVfVendorIdAndDeviceId

0x10000 - Vendor ID and Device ID

Device ID assigned by the

manufacturer of the device. On

power-up, the core sets it to the

value defined in the RTL file

reg_defaults.h. This field can be

written independently for each

Function from the local management

bus.

pub fn pcie_vf_command_and_status(&self) -> &PcieVfCommandAndStatus

0x10004 - Command and Status Register

This bit is set when the core has

received a Poisoned TLP targeted at

this VF. The Parity Error Response

enable bit (bit 6) in the PCI

Command Register of the associated

PF has no effect on the setting of

this bit. STICKY.

pub fn pcie_vf_revision_id_and_class_code( &self ) -> &PcieVfRevisionIdAndClassCode

0x10008 - Revision ID and Class Code Register

Identifies the function of the device.

This field reflects the setting of the

corresponding register in the

configuration space of the

associated Physical Function.

pub fn pcie_vf_bist_header_type_latency_timer_and_cache_line_size_s( &self ) -> &PcieVfBistHeaderTypeLatencyTimerAndCacheLineSizeS

0x1000c - BIST, Header Type, Latency Timer and Cache Line Size Registers

Reserved

pub fn pcie_vf_base_address_0(&self) -> &PcieVfBaseAddress0

0x10010 - Base Address Register 0

(no description)

pub fn pcie_vf_base_address_1(&self) -> &PcieVfBaseAddress1

0x10014 - Base Address Register 1

(no description)

pub fn pcie_vf_base_address_2(&self) -> &PcieVfBaseAddress2

0x10018 - Base Address Register 2

(no description)

pub fn pcie_vf_base_address_3(&self) -> &PcieVfBaseAddress3

0x1001c - Base Address Register 3

(no description)

pub fn pcie_vf_base_address_4(&self) -> &PcieVfBaseAddress4

0x10020 - Base Address Register 4

(no description)

pub fn pcie_vf_base_address_5(&self) -> &PcieVfBaseAddress5

0x10024 - Base Address Register 5

(no description)

pub fn pcie_vf_subsystem_vendor_id_and_subsystem_id( &self ) -> &PcieVfSubsystemVendorIdAndSubsystemId

0x1002c - Subsystem Vendor ID and Subsystem ID Register

Specifies the Subsystem ID assigned

by the manufacturer of the device.

This field reflects the setting of the

corresponding register in the

configuration space of the associated

Physical Function.

pub fn pcie_vf_expansion_rom_base_address( &self ) -> &PcieVfExpansionRomBaseAddress

0x10030 - Expansion ROM Base Address Register

(no description)

pub fn pcie_vf_capabilities_pointer(&self) -> &PcieVfCapabilitiesPointer

0x10034 - Capabilities Pointer

Reserved

pub fn pcie_vf_interrupt_line_and_interrupt_pin( &self ) -> &PcieVfInterruptLineAndInterruptPin

0x1003c - Interrupt Line and Interrupt Pin Register

(no description)

pub fn pcie_vf_power_management_capabilities( &self ) -> &PcieVfPowerManagementCapabilities

0x10080 - Power Management Capabilities Register

Indicates whether the Function is

capable of sending PME messages

when in the D3cold state. Because

the device does not have aux power,

this bit is hardwired to 0.

pub fn pcie_vf_power_management_control_status_report( &self ) -> &PcieVfPowerManagementControlStatusReport

0x10084 - Power Management Control/Status Report

This optional register is not

implemented in the PCIe core. This

field is hardwired to 0.

pub fn pcie_vf_msi_control(&self) -> &PcieVfMsiControl

0x10090 - MSI Control Register

Reserved

pub fn pcie_vf_msi_message_low_address(&self) -> &PcieVfMsiMessageLowAddress

0x10094 - MSI Message Low Address Register

Lower bits of the address to be used

in MSI messages. This field can also

be written from the local

management bus.

pub fn pcie_vf_msi_message_high_address(&self) -> &PcieVfMsiMessageHighAddress

0x10098 - MSI Message High Address Register

Contains bits 63:32 of the 64-bit

address to be used in MSI Messages.

A value of 0 specifies that 32-bit

addresses are to be used in the

messages. This field can also be

written from the local management

bus.

pub fn pcie_vf_msi_message_data(&self) -> &PcieVfMsiMessageData

0x1009c - MSI Message Data Register

Hardwired to 0

pub fn pcie_vf_msi_mask(&self) -> &PcieVfMsiMask

0x100a0 - MSI Mask Register

Please note that if the Multiple

Message Capable field is changed

from the local management APB bus,

then the width of this field also

changes correspondingly

pub fn pcie_vf_msi_pending_bits(&self) -> &PcieVfMsiPendingBits

0x100a4 - MSI Pending Bits Register

Please note that if the Multiple

Message Capable field is changed

from the local management APB bus,

then the width of this field also

changes correspondingly

pub fn pcie_vf_msi_x_control(&self) -> &PcieVfMsiXControl

0x100b0 - MSI-X Control Register

Set by the configuration program to

enable the MSI-X feature. This field

can also be written from the local

management bus.

pub fn pcie_vf_msi_x_table_offset(&self) -> &PcieVfMsiXTableOffset

0x100b4 - MSI-X Table Offset Register

Offset of the memory address where

the MSI- X Table is located,

relative to the selected BAR. The

three least significant bits of the

address are omitted, as the

addresses are QWORD aligned.

pub fn pcie_vf_msi_x_pending_interrupt(&self) -> &PcieVfMsiXPendingInterrupt

0x100b8 - MSI-X Pending Interrupt Register

Offset of the memory address where

the PBA is located, relative to the

selected BAR. The three least

significant bits of the address are

omitted, as the addresses are

QWORD aligned.

pub fn pcie_vf_pci_express_capability_list( &self ) -> &PcieVfPciExpressCapabilityList

0x100c0 - PCI Express Capability List Register

Reserved

pub fn pcie_vf_pci_express_device_capabilities( &self ) -> &PcieVfPciExpressDeviceCapabilities

0x100c4 - PCI Express Device Capabilities Register

Reserved

pub fn pcie_vf_pci_express_device_control_and_status( &self ) -> &PcieVfPciExpressDeviceControlAndStatus

0x100c8 - PCI Express Device Control and Status Register

Reserved

pub fn pcie_vf_link_capabilities(&self) -> &PcieVfLinkCapabilities

0x100cc - Link Capabilities Register

Specifies the port number assigned

to the PCI Express link connected to

this device.

pub fn pcie_vf_pci_express_device_capabilities_2( &self ) -> &PcieVfPciExpressDeviceCapabilities2

0x100e4 - PCI Express Device Capabilities Register 2

Reserved

pub fn pcie_vf_advanced_error_reporting_aer_enhanced_capability_header( &self ) -> &PcieVfAdvancedErrorReportingAerEnhancedCapabilityHeader

0x10100 - Advanced Error Reporting (AER) Enhanced Capability Header Register

Indicates offset to the next PCI

Express capability structure. The

default next pointer value is dynamic

and is dependent on whether the

strap or LMI bits are set.

pub fn pcie_vf_uncorrectable_error_status( &self ) -> &PcieVfUncorrectableErrorStatus

0x10104 - Uncorrectable Error Status Register

Reserved

pub fn pcie_vf_uncorrectable_error_mask(&self) -> &PcieVfUncorrectableErrorMask

0x10108 - Uncorrectable Error Mask Register

(no description)

pub fn pcie_vf_uncorrectable_error_severity( &self ) -> &PcieVfUncorrectableErrorSeverity

0x1010c - Uncorrectable Error Severity Register

(no description)

pub fn pcie_vf_correctable_error_status(&self) -> &PcieVfCorrectableErrorStatus

0x10110 - Correctable Error Status Register

Reserved

pub fn pcie_vf_correctable_error_mask(&self) -> &PcieVfCorrectableErrorMask

0x10114 - Correctable Error Mask Register

(no description)

pub fn pcie_vf_advanced_error_capabilities_and_control( &self ) -> &PcieVfAdvancedErrorCapabilitiesAndControl

0x10118 - Advanced Error Capabilities and Control Register

Reserved

pub fn pcie_vf_header_log_0(&self) -> &PcieVfHeaderLog0

0x1011c - Header Log Register 0

First DWORD of captured TLP header

STICKY.

pub fn pcie_vf_header_log_1(&self) -> &PcieVfHeaderLog1

0x10120 - Header Log Register 1

Second DWORD of captured TLP

header STICKY.

pub fn pcie_vf_header_log_2(&self) -> &PcieVfHeaderLog2

0x10124 - Header Log Register 2

Third DWORD of captured TLP

header STICKY.

pub fn pcie_vf_header_log_3(&self) -> &PcieVfHeaderLog3

0x10128 - Header Log Register 3

Fourth DWORD of captured TLP

header STICKY.

pub fn pcie_vf_ari_extended_capability_header( &self ) -> &PcieVfAriExtendedCapabilityHeader

0x10140 - ARI Extended Capability Header Register

Indicates offset to the next PCI

Express capability structure. The

default next pointer value is dynamic

and is dependent on whether the

strap or LMI bits are set.

pub fn pcie_vf_ari_capability_and_ari_control( &self ) -> &PcieVfAriCapabilityAndAriControl

0x10144 - ARI Capability Register and ARI Control Register

Reserved

pub fn pcie_vf_tph_requester_enhanced_capability_header( &self ) -> &PcieVfTphRequesterEnhancedCapabilityHeader

0x10274 - TPH Requester Enhanced Capability Header Register

Indicates offset to the next PCI

Express capability structure. The

default next pointer value is dynamic

and is dependent on whether the

strap or LMI bits are set.

pub fn pcie_vf_tph_requester_capability(&self) -> &PcieVfTphRequesterCapability

0x10278 - TPH Requester Capability Register

Reserved

pub fn pcie_vf_tph_requester_control(&self) -> &PcieVfTphRequesterControl

0x1027c - TPH Requester Control Register

Reserved

pub fn pcie_vf_tph_st_table_0(&self) -> &PcieVfTphStTable0

0x10280 - TPH ST Table 0

This field is used for the upper 8 bits

of the second Steering Tag when

Extended TPH Requester support is

enabled.

pub fn pcie_vf_tph_st_table_1(&self) -> &PcieVfTphStTable1

0x10284 - TPH ST Table 1

This field is used for the upper 8 bits

of the second Steering Tag when

Extended TPH Requester support is

enabled.

pub fn pcie_vf_tph_st_table_2(&self) -> &PcieVfTphStTable2

0x10288 - TPH ST Table 2

This field is used for the upper 8 bits

of the second Steering Tag when

Extended TPH Requester support is

enabled.

pub fn pcie_lm_physical_layer_configuration_0( &self ) -> &PcieLmPhysicalLayerConfiguration0

0x100000 - Physical Layer Configuration Register 0

When the core is operating as a Root

Port, setting this to 1 causes the

LTSSM to initiate a loopback and

become the loopback master. This

bit is not used in the EndPoint Mode.

pub fn pcie_lm_physical_layer_configuration_1( &self ) -> &PcieLmPhysicalLayerConfiguration1

0x100004 - Physical Layer Configuration Register 1

FTS count transmitted by the core in

TS1/TS2 sequences during link

training. This value must be set

based on the time needed by the

receiver to acquire sync while exiting

from L0S state.

pub fn pcie_lm_data_link_layer_timer_configuration( &self ) -> &PcieLmDataLinkLayerTimerConfiguration

0x100008 - Data Link Layer Timer Configuration Register

Reserved

pub fn pcie_lm_receive_credit_limit_0_vc0( &self ) -> &PcieLmReceiveCreditLimit0Vc0

0x10000c - Receive Credit Limit Register 0 VC0

Non-Posted payload credit limit

advertised by the core for VC 0 (in

units of 4 Dwords).

pub fn pcie_lm_receive_credit_limit_1_vc0( &self ) -> &PcieLmReceiveCreditLimit1Vc0

0x100010 - Receive Credit Limit Register 1 VC0

Completion header credit limit

advertised by the core for VC 0 (in

number of packets).

pub fn pcie_lm_transmit_credit_limit_0_vc0( &self ) -> &PcieLmTransmitCreditLimit0Vc0

0x100014 - Transmit Credit Limit Register 0 VC0

Non-Posted payload credit limit

received by the core for Link 0 (in

units of 4 Dwords).

pub fn pcie_lm_transmit_credit_limit_1_vc0( &self ) -> &PcieLmTransmitCreditLimit1Vc0

0x100018 - Transmit Credit Limit Register 1 VC0

Completion header credit limit

received by the core for VC 0 (in

number of packets).

pub fn pcie_lm_transmit_credit_update_interval_configuration_0( &self ) -> &PcieLmTransmitCreditUpdateIntervalConfiguration0

0x10001c - Transmit Credit Update Interval Configuration Register 0

Minimum credit update interval for

non-posted transactions. The core

follows this minimum interval

between issuing posted credit

updates on the link. This is to limit

the bandwidth use of credit updates.

If new credit becomes available in

the receive FIFO since the last

update was sent, the core will issue

a new update only after this interval

has elapsed since the last update.

The value is in units of 4 ns. This

field is re-written by the internal

logic when the negotiated link width

or link speed changes, to correspond

to the default values defined in

defines.h. The user may override this

default value by writing into this

register field. The value written will

be lost on a change in the negotiated

link width/speed.

pub fn pcie_lm_transmit_credit_update_interval_configuration_1( &self ) -> &PcieLmTransmitCreditUpdateIntervalConfiguration1

0x100020 - Transmit Credit Update Interval Configuration Register 1

Maximum credit update interval for

all transactions. If no new credit has

become available since the last

update, the core will repeat the last

update after this interval. This is to

recover from any losses of credit

update packets. The value is in units

of 4 ns. This field could be re-written

by the internal logic when the

negotiated link width or link speed

changes, to correspond to the

default values defined in defines.h.

The user may override this default

value by writing into this register

field. The value written will be lost

on a change in the negotiated link

width/speed.

pub fn pcie_lm_l0s_timeout_limit(&self) -> &PcieLmL0sTimeoutLimit

0x100024 - L0S Timeout Limit Register

Reserved

pub fn pcie_lm_transmit_tlp_count(&self) -> &PcieLmTransmitTlpCount

0x100028 - Transmit TLP Count Register

Count of TLPs transmitted

pub fn pcie_lm_transmit_tlp_payload_dword_count( &self ) -> &PcieLmTransmitTlpPayloadDwordCount

0x10002c - Transmit TLP Payload Dword Count Register

Count of TLPs payload Dwords

transmitted

pub fn pcie_lm_receive_tlp_count(&self) -> &PcieLmReceiveTlpCount

0x100030 - Receive TLP Count Register

Count of TLPs received

pub fn pcie_lm_receive_tlp_payload_dword_count( &self ) -> &PcieLmReceiveTlpPayloadDwordCount

0x100034 - Receive TLP Payload Dword Count Register

Count of TLP payload Dwords

received

pub fn pcie_lm_completion_timeout_limit_0( &self ) -> &PcieLmCompletionTimeoutLimit0

0x100038 - Completion Timeout Limit Register 0

Reserved

pub fn pcie_lm_completion_timeout_limit_1( &self ) -> &PcieLmCompletionTimeoutLimit1

0x10003c - Completion Timeout Limit Register 1

Reserved

pub fn pcie_lm_l1_state_re_entry_delay(&self) -> &PcieLmL1StateReEntryDelay

0x100040 - L1 State Re-Entry Delay Register

Delay to re-enter L1 after no activity

(in units of 4 ns).

pub fn pcie_lm_vendor_id(&self) -> &PcieLmVendorId

0x100044 - Vendor ID Register

Subsystem Vendor ID

pub fn pcie_lm_aspm_l1_entry_timeout_delay( &self ) -> &PcieLmAspmL1EntryTimeoutDelay

0x100048 - ASPM L1 Entry Timeout Delay Register

Reserved

pub fn pcie_lm_pme_turnoff_ack_delay(&self) -> &PcieLmPmeTurnoffAckDelay

0x10004c - PME TurnOff Ack Delay Register

Reserved

pub fn pcie_lm_linkwidth_control(&self) -> &PcieLmLinkwidthControl

0x100050 - Linkwidth Control Register

Reserved

pub fn pcie_lm_sris_control(&self) -> &PcieLmSrisControl

0x100074 - SRIS Control Register

Reserved

pub fn pcie_lm_shadow_register_header_log_0( &self ) -> &PcieLmShadowRegisterHeaderLog0

0x100100 - Shadow register header log 0

The value here will be reflected in

the target function’s header log

register when f/w sets any bit In

the shadow error register. If the

header log is already set in the

function’s AER space, the value

here may not get written and a

header log overflow bit would get

set. This register holds [31:0]

value of the TLP header.

pub fn pcie_lm_shadow_register_header_log_1( &self ) -> &PcieLmShadowRegisterHeaderLog1

0x100104 - Shadow register header log 1

The value here will be reflected in

the target function’s header log

register when f/w sets any bit In

the shadow error register. If the

header log is already set in the

function’s AER space, the value

here may not get written and a

header log overflow bit would get

set. This register holds [63:32]

value of the TLP header.

pub fn pcie_lm_shadow_register_header_log_2( &self ) -> &PcieLmShadowRegisterHeaderLog2

0x100108 - Shadow register header log 2

The value here will be reflected in

the target function’s header log

register when f/w sets any bit In

the shadow error register. If the

header log is already set in the

function’s AER space, the value

here may not get written and a

header log overflow bit would get

set. This register holds [95:64]

value of the TLP header.

pub fn pcie_lm_shadow_register_header_log_3( &self ) -> &PcieLmShadowRegisterHeaderLog3

0x10010c - Shadow register header log 3

The value here will be reflected in

the target function’s header log

register when f/w sets any bit In

the shadow error register. If the

header log is already set in the

function’s AER space, the value

here may not get written and a

header log overflow bit would get

set. This register holds [127:96]

value of the TLP header.

pub fn pcie_lm_shadow_register_function_number( &self ) -> &PcieLmShadowRegisterFunctionNumber

0x100110 - Shadow register function number.

Reserved

pub fn pcie_lm_shadow_ur_error(&self) -> &PcieLmShadowUrError

0x100114 - Shadow Register UR Error

Reserved

pub fn pcie_lm_negotiated_lane_map(&self) -> &PcieLmNegotiatedLaneMap

0x100200 - Negotiated Lane Map Register

Reserved

pub fn pcie_lm_receive_fts_count(&self) -> &PcieLmReceiveFtsCount

0x100204 - Receive FTS Count Register

Reserved

pub fn pcie_lm_debug_mux_control(&self) -> &PcieLmDebugMuxControl

0x100208 - Debug Mux Control Register

Setting this bit to 0 causes all the

enabled Functions to report an error

when a Type-1 configuration access

is received by the core, targeted at

any Function. Setting it to 1 limits

the error reporting to the type-0

Function whose number matches

with the Function number specified

in the request. If the Function

number in the request refers to an

unimplemented or disabled

Function, all enabled Functions

report the error regardless of the

setting of this bit.

pub fn pcie_lm_local_error_and_status(&self) -> &PcieLmLocalErrorAndStatus

0x10020c - Local Error and Status Register

Reserved

pub fn pcie_lm_local_interrupt_mask(&self) -> &PcieLmLocalInterruptMask

0x100210 - Local Interrupt Mask Register

Reserved

pub fn pcie_lm_lcrc_error_count(&self) -> &PcieLmLcrcErrorCount

0x100214 - LCRC Error Count Register

Reserved

pub fn pcie_lm_ecc_correctable_error_count( &self ) -> &PcieLmEccCorrectableErrorCount

0x100218 - ECC Correctable Error Count Register

Number of correctable errors

detected while reading from the TPH

Steering Tag RAM. This is an 8-bit

saturating counter that can be

cleared by writing all 1s into it.

pub fn pcie_lm_ltr_snoop_no_snoop_latency( &self ) -> &PcieLmLtrSnoopNoSnoopLatency

0x10021c - LTR Snoop/No-Snoop Latency Register

The client software must set this bit

to 1 to set the Snoop Latency

Requirement bit in the LTR message

to be sent.

pub fn pcie_lm_ltr_message_generation_control( &self ) -> &PcieLmLtrMessageGenerationControl

0x100220 - LTR Message Generation Control Register

RSVD

pub fn pcie_lm_pme_service_timeout_delay(&self) -> &PcieLmPmeServiceTimeoutDelay

0x100224 - PME Service Timeout Delay Register

Reserved

pub fn pcie_lm_root_port_requestor_id(&self) -> &PcieLmRootPortRequestorId

0x100228 - Root Port Requestor ID Register

Reserved

pub fn pcie_lm_end_point_bus_and_device_number( &self ) -> &PcieLmEndPointBusAndDeviceNumber

0x10022c - End Point Bus and Device Number Register

Reserved

pub fn pcie_lm_physical_function_bar_configuration_0( &self ) -> &PcieLmPhysicalFunctionBarConfiguration0

0x100240 - Physical Function BAR Configuration Register 0

Specifies the configuration of BAR3.

The various encodings are: 000:

Disabled 001: 32bit IO BAR 010-

011: Reserved 100: 32bit memory

BAR, non prefetchable 101: 32bit

memory BAR, prefetchable 110-111:

Reserved

pub fn pcie_lm_physical_function_bar_configuration_1( &self ) -> &PcieLmPhysicalFunctionBarConfiguration1

0x100244 - Physical Function BAR Configuration Register 1

Setting this bit to 1 enables the

Resizable BAR Capability in the PCI

Express Configuration Space of the

associated Function. When the

Resizable BAR Capability is enabled,

the apertures of the memory BARs of

the corresponding Function are no

longer selected by the fields in this

register, but by the setting of the

registers in the Resizable BAR

Capability Structure.

pub fn pcie_lm_virtual_function_bar_configuration_0( &self ) -> &PcieLmVirtualFunctionBarConfiguration0

0x100280 - Virtual Function BAR Configuration Register 0

Specifies the configuration of VF

BAR3. The various encodings are:

000: Disabled 001-011: Reserved

100: 32bit memory BAR, non

prefetchable 101: 32bit memory

BAR, prefetchable 110-111:

Reserved

pub fn pcie_lm_virtual_function_bar_configuration_1( &self ) -> &PcieLmVirtualFunctionBarConfiguration1

0x100284 - Virtual Function BAR Configuration Register 1

Reserved

pub fn pcie_lm_physical_function_configuration( &self ) -> &PcieLmPhysicalFunctionConfiguration

0x1002c0 - Physical Function Configuration Register

Reserved

pub fn pcie_lm_root_complex_bar_configuration( &self ) -> &PcieLmRootComplexBarConfiguration

0x100300 - Root Complex BAR Configuration Register

This bit must be set to 1 to enable

BAR checking in the RC mode. When

this bit is set to 0, the core will

forward all incoming memory

requests to the client logic without

checking their address ranges.

pub fn pcie_rc_vendor_id_and_device_id(&self) -> &PcieRcVendorIdAndDeviceId

0x200000 - Vendor ID and Device ID

Device ID assigned by the

manufacturer of the device. On

power-up, the core sets it to the

value defined in the RTL file

reg_defaults.h. This field can be

written from the APB bus by setting

[21] bit high of the

pcie_mgmt_APB_ADDR during a

local management register write.

pub fn pcie_rc_command_and_status(&self) -> &PcieRcCommandAndStatus

0x200004 - Command and Status Register

This bit is set when the core has

received a poisoned TLP. The Parity

Error Response enable bit (bit 6) has

no effect on the setting of this bit.

This field can also be cleared from

the local management bus APB by

writing a 1 into this bit position. This

field can be forced to 1 from the

APB bus by setting [21] bit high of

the pcie_mgmt_APB_ADDR during a

local management register write.

pub fn pcie_rc_revision_id_and_class_code( &self ) -> &PcieRcRevisionIdAndClassCode

0x200008 - Revision ID and Class Code Register

Identifies the function of the device.

On power- up, the core sets it to the

value defined in the RTL file

reg_defaults.h. This field can be

written from the APB bus by setting

[21] bit high of the

pcie_mgmt_APB_ADDR during a

local management register write.

pub fn pcie_rc_bist_header_type_latency_timer_and_cache_line_size_s( &self ) -> &PcieRcBistHeaderTypeLatencyTimerAndCacheLineSizeS

0x20000c - BIST, Header Type, Latency Timer and Cache Line Size Registers

BIST control register. This field can

be written from the APB bus by

setting [21] bit high of the

pcie_mgmt_APB_ADDR during a

local management register write.

pub fn pcie_rc_root_complex_base_address_0( &self ) -> &PcieRcRootComplexBaseAddress0

0x200010 - Root Complex Base Address Register 0

This field defines the base address

of the memory address range. The

number of implemented bits in this

field determines the BAR aperture

configured in Root Complex BAR

Configuration Register. All other bits

are not writeable, and are read as

0’s.

pub fn pcie_rc_root_complex_base_address_1( &self ) -> &PcieRcRootComplexBaseAddress1

0x200014 - Root Complex Base Address Register 1

This field defines the base address of

the memory address range. The

number of implemented bits in this

field determines the BAR aperture

configured in Root Complex BAR

Configuration Register. All other bits

are not writeable, and are read as

0’s.

pub fn pcie_rc_primary_bus_number_secondary_bus_number_subordinate_bus_number_secondary_latency_timer( &self ) -> &PcieRcPrimaryBusNumberSecondaryBusNumberSubordinateBusNumberSecondaryLatencyTimer

0x200018 - Primary Bus Number, Secondary Bus Number, Subordinate Bus Number, Secondary Latency Timer

This field is not implemented.

pub fn pcie_rc_io_base_io_limit_secondary_status( &self ) -> &PcieRcIoBaseIoLimitSecondaryStatus

0x20001c - IO Base, IO Limit, Secondary Status Register

The core does not set this bit by

itself. This bit can be cleared by

writing a 1 into this bit position from

the local management APB bus. This

field can be forced to 1 or 0 from the

APB bus by setting [21] bit high of

the pcie_mgmt_APB_ADDR during a

local management register write.

pub fn pcie_rc_memory_base_memory_limit(&self) -> &PcieRcMemoryBaseMemoryLimit

0x200020 - Memory Base, Memory Limit

This field can be read and written

from the local management APB bus,

but its value is not used within the

core.

pub fn pcie_rc_prefetchable_memory_base_prefetchable_memory_limit( &self ) -> &PcieRcPrefetchableMemoryBasePrefetchableMemoryLimit

0x200024 - Prefetchable Memory Base, Prefetchable Memory Limit

This field can be read and written

from the local management APB bus

if prefetchable memory is enabled in

the Root Complex BAR configuration

register, else it is hardwired to zero.

Its value is not used within the core.

pub fn pcie_rc_prefetchable_base_upper(&self) -> &PcieRcPrefetchableBaseUpper

0x200028 - Prefetchable Base Upper

This field can be read and written

from the local management APB bus

if 64bit prefetchable memory is

enabled in the Root Complex BAR

configuration register, else it is

hardwired to zero. Its value is not

used within the core.

pub fn pcie_rc_prefetchable_limit_upper(&self) -> &PcieRcPrefetchableLimitUpper

0x20002c - Prefetchable Limit Upper

This field can be read and written

from the local management APB bus

if 64bit prefetchable memory is

enabled in the Root Complex BAR

configuration register, else it is

hardwired to zero. Its value is not

used within the core.

pub fn pcie_rc_io_base_upper_io_limit_upper( &self ) -> &PcieRcIoBaseUpperIoLimitUpper

0x200030 - IO Base Upper, IO Limit Upper

This field can be read and written

from the local management bus if

32bit IO BAR is enabled in the Root

Complex BAR configuration register,

else it is hardwired to zero. Its value

is not used within the core.

pub fn pcie_rc_capabilities_pointer(&self) -> &PcieRcCapabilitiesPointer

0x200034 - Capabilities Pointer

Reserved

pub fn pcie_rc_interrupt_line_interrupt_pin_and_bridge_control( &self ) -> &PcieRcInterruptLineInterruptPinAndBridgeControl

0x20003c - Interrupt Line, Interrupt Pin Register and Bridge Control Register

Reserved

pub fn pcie_rc_power_management_capabilities( &self ) -> &PcieRcPowerManagementCapabilities

0x200080 - Power Management Capabilities Register

Indicates whether the Function is

capable of sending PME messages

when in the D3cold state. This field

can be written from the APB bus by

setting [21] bit high of the

pcie_mgmt_APB_ADDR during a

local management register write.

pub fn pcie_rc_power_management_control_status_report( &self ) -> &PcieRcPowerManagementControlStatusReport

0x200084 - Power Management Control/Status Report

This optional register is not

implemented in the PCIe core. This

field is hardwired to 0.

pub fn pcie_rc_msi_control(&self) -> &PcieRcMsiControl

0x200090 - MSI Control Register

Reserved

pub fn pcie_rc_msi_message_low_address(&self) -> &PcieRcMsiMessageLowAddress

0x200094 - MSI Message Low Address Register

Lower bits of the address to be used

in MSI messages. This field can also

be written from the local

management bus.

pub fn pcie_rc_msi_message_high_address(&self) -> &PcieRcMsiMessageHighAddress

0x200098 - MSI Message High Address Register

Contains bits 63:32 of the 64-bit

address to be used in MSI Messages.

A value of 0 specifies that 32-bit

addresses are to be used in the

messages. This field can also be

written from the local management

bus.

pub fn pcie_rc_msi_message_data(&self) -> &PcieRcMsiMessageData

0x20009c - MSI Message Data Register

Hardwired to 0

pub fn pcie_rc_msi_mask(&self) -> &PcieRcMsiMask

0x2000a0 - MSI Mask Register

RSVD

pub fn pcie_rc_msi_pending_bits(&self) -> &PcieRcMsiPendingBits

0x2000a4 - MSI Pending Bits Register

RSVD

pub fn pcie_rc_msi_x_control(&self) -> &PcieRcMsiXControl

0x2000b0 - MSI-X Control Register

Set by the configuration program to

enable the MSI-X feature. This field

can also be written from the local

management bus.

pub fn pcie_rc_msi_x_table_offset(&self) -> &PcieRcMsiXTableOffset

0x2000b4 - MSI-X Table Offset Register

Offset of the memory address where

the MSI- X Table is located, relative

to the selected BAR. The three least

significant bits of the address are

omitted, as the addresses are

QWORD aligned.

pub fn pcie_rc_msi_x_pending_interrupt(&self) -> &PcieRcMsiXPendingInterrupt

0x2000b8 - MSI-X Pending Interrupt Register

Offset of the memory address where

the PBA is located, relative to the

selected BAR. The three least

significant bits of the address are

omitted, as the addresses are

QWORD aligned.

pub fn pcie_rc_pci_express_capability_list( &self ) -> &PcieRcPciExpressCapabilityList

0x2000c0 - PCI Express Capability List Register

Reserved

pub fn pcie_rc_pci_express_device_capabilities( &self ) -> &PcieRcPciExpressDeviceCapabilities

0x2000c4 - PCI Express Device Capabilities Register

Reserved

pub fn pcie_rc_pci_express_device_control_and_status( &self ) -> &PcieRcPciExpressDeviceControlAndStatus

0x2000c8 - PCI Express Device Control and Status Register

(no description)

pub fn pcie_rc_link_capabilities(&self) -> &PcieRcLinkCapabilities

0x2000cc - Link Capabilities Register

Specifies the port number assigned

to the PCI Express link connected to

this device. This field can be written

from the APB bus by setting [21] bit

high of the pcie_mgmt_APB_ADDR

during a local management register

write.

pub fn pcie_rc_link_control_and_status(&self) -> &PcieRcLinkControlAndStatus

0x2000d0 - Link Control and Status Register

This bit is Set by hardware to

indicate that hardware has

autonomously changed Link speed

or width, without the Port

transitioning through DL_Down

status, for reasons other than to

attempt to correct unreliable Link

operation. This triggers an interrupt

to be generated through

PHY_INTERRUPT_OUT if enabled.

Hardwired to 0 if Link Bandwidth

Notification Capability is 0.

pub fn pcie_rc_slot_capability(&self) -> &PcieRcSlotCapability

0x2000d4 - Slot Capability Register

This field indicates the physical

slot number attached to this Port.

This field must be hardware

initialized to a value that assigns

a slot number that is unique

within the chassis, regardless of

the form factor associated with

the slot. This field must be

initialized to zero for Ports

connected to devices that are

either integrated on the system

board or integrated within the

same silicon as the Switch device

or Root Port.

pub fn pcie_rc_slot_control_and_status(&self) -> &PcieRcSlotControlAndStatus

0x2000d8 - Slot Control and Status Register

(no description)

pub fn pcie_rc_root_control_and_capability( &self ) -> &PcieRcRootControlAndCapability

0x2000dc - Root Control and Capability Register

Reserved

pub fn pcie_rc_root_status(&self) -> &PcieRcRootStatus

0x2000e0 - Root Status Register

Reserved

pub fn pcie_rc_pci_express_device_capabilities_2( &self ) -> &PcieRcPciExpressDeviceCapabilities2

0x2000e4 - PCI Express Device Capabilities 2 Register

Reserved

pub fn pcie_rc_pci_express_device_control_and_status_2( &self ) -> &PcieRcPciExpressDeviceControlAndStatus2

0x2000e8 - PCI Express Device Control and Status 2 Register

(no description)

pub fn pcie_rc_link_capabilities_2(&self) -> &PcieRcLinkCapabilities2

0x2000ec - Link Capabilities Register 2

RSVD

pub fn pcie_rc_link_control_and_status_2(&self) -> &PcieRcLinkControlAndStatus2

0x2000f0 - Link Control and Status 2 Register

Reserved

pub fn pcie_rc_advanced_error_reporting_aer_enhanced_capability_header( &self ) -> &PcieRcAdvancedErrorReportingAerEnhancedCapabilityHeader

0x200100 - Advanced Error Reporting (AER) Enhanced Capability Header Register

Indicates offset to the next PCI

Express capability structure. The

default next pointer value is dynamic

and is dependent on whether the

strap or LMI bits are set.

pub fn pcie_rc_uncorrectable_error_status( &self ) -> &PcieRcUncorrectableErrorStatus

0x200104 - Uncorrectable Error Status Register

Reserved

pub fn pcie_rc_uncorrectable_error_mask(&self) -> &PcieRcUncorrectableErrorMask

0x200108 - Uncorrectable Error Mask Register

Reserved

pub fn pcie_rc_uncorrectable_error_severity( &self ) -> &PcieRcUncorrectableErrorSeverity

0x20010c - Uncorrectable Error Severity Register

(no description)

pub fn pcie_rc_correctable_error_status(&self) -> &PcieRcCorrectableErrorStatus

0x200110 - Correctable Error Status Register

Reserved

pub fn pcie_rc_correctable_error_mask(&self) -> &PcieRcCorrectableErrorMask

0x200114 - Correctable Error Mask Register

Reserved

pub fn pcie_rc_advanced_error_capabilities_and_control( &self ) -> &PcieRcAdvancedErrorCapabilitiesAndControl

0x200118 - Advanced Error Capabilities and Control Register

Reserved

pub fn pcie_rc_header_log_0(&self) -> &PcieRcHeaderLog0

0x20011c - Header Log Register 0

First Dword of captured TLP header.

STICKY.

pub fn pcie_rc_header_log_1(&self) -> &PcieRcHeaderLog1

0x200120 - Header Log Register 1

Second Dword of captured TLP

header. STICKY.

pub fn pcie_rc_header_log_2(&self) -> &PcieRcHeaderLog2

0x200124 - Header Log Register 2

Third Dword of captured TLP header.

STICKY.

pub fn pcie_rc_header_log_3(&self) -> &PcieRcHeaderLog3

0x200128 - Header Log Register 3

Fourth Dword of captured TLP

header. STICKY.

pub fn pcie_rc_root_error_command(&self) -> &PcieRcRootErrorCommand

0x20012c - Root Error Command Register

Reserved

pub fn pcie_rc_root_error_status(&self) -> &PcieRcRootErrorStatus

0x200130 - Root Error Status Register

Reserved

pub fn pcie_rc_error_source_identification( &self ) -> &PcieRcErrorSourceIdentification

0x200134 - Error Source Identification Register

This field captures and stores the

Requester ID from an ERR_FATAL or

ERROR_NONFATAL message

received by the RC, if the

ERR_FATAL or NONFATAL Received

bit was not set at the time the

message was received. STICKY

pub fn pcie_rc_tph_st_table_3(&self) -> &PcieRcTphStTable3

0x200280 - TPH ST Table 3

This field is used for the upper 8 bits

of the second Steering Tag when

Extended TPH Requester support is

enabled.

pub fn pcie_rc_l1_pm_substates_extended_capability_header( &self ) -> &PcieRcL1PmSubstatesExtendedCapabilityHeader

0x200900 - L1 PM Substates Extended Capability Header Register

Indicates offset to the next PCI

Express capability structure. The

default next pointer value is dynamic

and is dependent on whether the

strap or LMI bits are set.

pub fn pcie_rc_l1_pm_substates_capabilities( &self ) -> &PcieRcL1PmSubstatesCapabilities

0x200904 - L1 PM Substates Capabilities Register

RSVD

pub fn pcie_rc_l1_pm_substates_control_1(&self) -> &PcieRcL1PmSubstatesControl1

0x200908 - L1 PM Substates Control 1 Register

(no description)

pub fn pcie_rc_l1_pm_substates_control_2(&self) -> &PcieRcL1PmSubstatesControl2

0x20090c - L1 PM Substates Control 2 Register

RSVD

pub fn pcie_at_ob_outbound_region_address_0( &self ) -> &PcieAtObOutboundRegionAddress0

0x400000 - Outbound Region Address 0

Lower 32-bits of Address Register

for region N

pub fn pcie_at_ob_outbound_region_address_1( &self ) -> &PcieAtObOutboundRegionAddress1

0x400004 - Outbound Region Address 1

Upper 32-bits of Address Register

for region N

pub fn pcie_at_ob_outbound_region_descriptor_0( &self ) -> &PcieAtObOutboundRegionDescriptor0

0x400008 - Outbound Region Descriptor 0

Lowest 32-bits of Address Register

for region N

pub fn pcie_at_ob_outbound_region_descriptor_1( &self ) -> &PcieAtObOutboundRegionDescriptor1

0x40000c - Outbound Region Descriptor 1

Lower middle 32-bits of Address

Register for region N

pub fn pcie_at_ob_outbound_region_descriptor_2( &self ) -> &PcieAtObOutboundRegionDescriptor2

0x400010 - Outbound Region Descriptor 2

Upper middle 32-bits of Address

Register for region N

pub fn pcie_at_ob_outbound_region_descriptor_3( &self ) -> &PcieAtObOutboundRegionDescriptor3

0x400014 - Outbound Region Descriptor 3

Upmost 32-bits of Address Register

for region N

pub fn pcie_at_rp_ib_rp_inbound_bar_address_translation_0( &self ) -> &PcieAtRpIbRpInboundBarAddressTranslation0

0x400800 - RP Inbound BAR Address Translation 0

Bits [31:8] of Address Register for

BAR N

pub fn pcie_at_rp_ib_rp_inbound_bar_address_translation_1( &self ) -> &PcieAtRpIbRpInboundBarAddressTranslation1

0x400804 - RP Inbound BAR Address Translation 1

Bits [63:32] of Address Register for

BAR N

pub fn pcie_at_rp_ib_link_down_indication_bit( &self ) -> &PcieAtRpIbLinkDownIndicationBit

0x400824 - Link down indication bit

RSVD

pub fn pcie_at_ep_ib_ep_inbound_bar_address_translation_0( &self ) -> &PcieAtEpIbEpInboundBarAddressTranslation0

0x400828 - EP Inbound BAR Address Translation 0

Bits [31:0] of Address Register for

BAR N

pub fn pcie_at_ep_ib_ep_inbound_bar_address_translation_1( &self ) -> &PcieAtEpIbEpInboundBarAddressTranslation1

0x40082c - EP Inbound BAR Address Translation 1

Bits [63:32] of Address Register for

BAR N

pub fn pcie_dma_channel_0_control(&self) -> &PcieDmaChannel0Control

0x600000 - PCIe DMA Channel 0 Control Register

Reserved for future use

pub fn pcie_dma_channel_0_start_pointer_lower( &self ) -> &PcieDmaChannel0StartPointerLower

0x600004 - PCIe DMA Channel 0 Start Pointer Lower Register

Lower 32-bits Pointer Address

Registers

pub fn pcie_dma_channel_0_start_pointer_upper( &self ) -> &PcieDmaChannel0StartPointerUpper

0x600008 - PCIe DMA Channel 0 Start Pointer Upper Register

Upper 32-bits Pointer Address

Registers

pub fn pcie_dma_channel_0_attribute_lower( &self ) -> &PcieDmaChannel0AttributeLower

0x60000c - PCIe DMA Channel 0 Attribute Lower Register

Lower 32-bits Attribute Values used

when fetching and returning link list

descriptors

pub fn pcie_dma_channel_0_attribute_upper( &self ) -> &PcieDmaChannel0AttributeUpper

0x600010 - PCIe DMA Channel 0 Attribute Upper Register

Upper 32-bit Attribute Values used

when fetching and returning link list

descriptors

pub fn pcie_dma_channel_1_control(&self) -> &PcieDmaChannel1Control

0x600014 - PCIe DMA Channel 1 Control Register

Reserved for future use

pub fn pcie_dma_channel_1_start_pointer_lower( &self ) -> &PcieDmaChannel1StartPointerLower

0x600018 - PCIe DMA Channel 1 Start Pointer Lower Register

Lower 32-bits Pointer Address

Registers

pub fn pcie_dma_channel_1_start_pointer_upper( &self ) -> &PcieDmaChannel1StartPointerUpper

0x60001c - PCIe DMA Channel 1 Start Pointer Upper Register

Upper 32-bits Pointer Address

Registers

pub fn pcie_dma_channel_1_attribute_lower( &self ) -> &PcieDmaChannel1AttributeLower

0x600020 - PCIe DMA Channel 1 Attribute Lower Register

Lower 32-bits Attribute Values used

when fetching and returning link list

descriptors

pub fn pcie_dma_channel_1_attribute_upper( &self ) -> &PcieDmaChannel1AttributeUpper

0x600024 - PCIe DMA Channel 1 Attribute Upper Register

Upper 32-bit Attribute Values used

when fetching and returning link list

descriptors

pub fn pcie_dma_interrupt(&self) -> &PcieDmaInterrupt

0x6000a0 - PCIe DMA Interrupt Register

pub fn pcie_dma_interrupt_enable(&self) -> &PcieDmaInterruptEnable

0x6000a4 - PCIe DMA Interrupt Enable Register

pub fn pcie_dma_interrupt_disable(&self) -> &PcieDmaInterruptDisable

0x6000a8 - PCIe DMA Interrupt Disable Register

pub fn pcie_dma_inbound_buffer_uncorrected_ecc_errors( &self ) -> &PcieDmaInboundBufferUncorrectedEccErrors

0x6000ac - PCIe DMA Inbound Buffer Uncorrected ECC Errors

Reserved for future use

pub fn pcie_dma_inbound_buffer_corrected_ecc_errors( &self ) -> &PcieDmaInboundBufferCorrectedEccErrors

0x6000b0 - PCIe DMA Inbound Buffer corrected ECC Errors

Reserved for future use

pub fn pcie_dma_outbound_buffer_uncorrected_ecc_errors( &self ) -> &PcieDmaOutboundBufferUncorrectedEccErrors

0x6000b4 - PCIe DMA Outbound Buffer Uncorrected ECC Errors

Reserved for future use

pub fn pcie_dma_outbound_buffer_corrected_ecc_errors( &self ) -> &PcieDmaOutboundBufferCorrectedEccErrors

0x6000b8 - PCIe DMA Outbound Buffer corrected ECC Errors

Reserved for future use

pub fn pcie_dma_capability_and_version(&self) -> &PcieDmaCapabilityAndVersion

0x6000f8 - PCIe DMA Capability and Version Register

Reserved for future use

pub fn pcie_dma_configuration(&self) -> &PcieDmaConfiguration

0x6000fc - PCIe DMA Configuration Register

Reserved for future use

Trait Implementations

impl Debug for PcieCore

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Deref for PcieCore

type Target = RegisterBlock

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl Send for PcieCore