Struct rk3399_pac::DdrMon
source · pub struct DdrMon { /* private fields */ }
Expand description
DDR Monitor (DDR_MON) Registers
Implementations§
source§impl DdrMon
impl DdrMon
sourcepub const PTR: *const RegisterBlock = {0xff630000 as *const ddr_mon::RegisterBlock}
pub const PTR: *const RegisterBlock = {0xff630000 as *const ddr_mon::RegisterBlock}
Pointer to the register block
sourcepub const fn ptr() -> *const RegisterBlock
pub const fn ptr() -> *const RegisterBlock
Return the pointer to the register block
sourcepub unsafe fn steal() -> Self
pub unsafe fn steal() -> Self
Steal an instance of this peripheral
§Safety
Ensure that the new instance of the peripheral cannot be used in a way that may race with any existing instances, for example by only accessing read-only or write-only registers, or by consuming the original peripheral and using critical sections to coordinate access between multiple new instances.
Additionally, other software such as HALs may rely on only one peripheral instance existing to ensure memory safety; ensure no stolen instances are passed to such software.
Methods from Deref<Target = RegisterBlock>§
sourcepub fn ip_version(&self) -> &IpVersion
pub fn ip_version(&self) -> &IpVersion
0x00 - DDR Monitor IP Version
sourcepub fn int_status(&self) -> &IntStatus
pub fn int_status(&self) -> &IntStatus
0x08 - Interrupt Status
sourcepub fn timer_count(&self) -> &TimerCount
pub fn timer_count(&self) -> &TimerCount
0x10 - The DFI Timer Threshold
sourcepub fn floor_number(&self) -> &FloorNumber
pub fn floor_number(&self) -> &FloorNumber
0x14 - The Low Threshold in the Comparison of DDR Access
sourcepub fn top_number(&self) -> &TopNumber
pub fn top_number(&self) -> &TopNumber
0x18 - The High Threshold in the Comparison of DDR Access
sourcepub fn ch0_dfi_act_num(&self) -> &Ch0DfiActNum
pub fn ch0_dfi_act_num(&self) -> &Ch0DfiActNum
0x1c - Channel 0 DFI Active Command Number
sourcepub fn ch0_dfi_wr_num(&self) -> &Ch0DfiWrNum
pub fn ch0_dfi_wr_num(&self) -> &Ch0DfiWrNum
0x20 - Channel 0 DFI write Command Number
sourcepub fn ch0_dfi_rd_num(&self) -> &Ch0DfiRdNum
pub fn ch0_dfi_rd_num(&self) -> &Ch0DfiRdNum
0x24 - Channel 0 DFI read Command Number
sourcepub fn ch0_count_num(&self) -> &Ch0CountNum
pub fn ch0_count_num(&self) -> &Ch0CountNum
0x28 - Channel 0 Timer Count Number
sourcepub fn ch0_dfi_access_num(&self) -> &Ch0DfiAccessNum
pub fn ch0_dfi_access_num(&self) -> &Ch0DfiAccessNum
0x2c - Channel 0 DFI Read and Write Command Number
sourcepub fn ch1_dfi_act_num(&self) -> &Ch1DfiActNum
pub fn ch1_dfi_act_num(&self) -> &Ch1DfiActNum
0x30 - Channel 1 DFI Active Command Number
sourcepub fn ch1_dfi_wr_num(&self) -> &Ch1DfiWrNum
pub fn ch1_dfi_wr_num(&self) -> &Ch1DfiWrNum
0x34 - Channel 1 DFI write Command Number
sourcepub fn ch1_dfi_rd_num(&self) -> &Ch1DfiRdNum
pub fn ch1_dfi_rd_num(&self) -> &Ch1DfiRdNum
0x38 - Channel 1 DFI read Command Number
sourcepub fn ch1_count_num(&self) -> &Ch1CountNum
pub fn ch1_count_num(&self) -> &Ch1CountNum
0x3c - Channel 1 Timer Count Number
sourcepub fn ch1_dfi_access_num(&self) -> &Ch1DfiAccessNum
pub fn ch1_dfi_access_num(&self) -> &Ch1DfiAccessNum
0x40 - Channel 1 DFI Read and Write Command Number
sourcepub fn ddr_if_ctrl(&self) -> &DdrIfCtrl
pub fn ddr_if_ctrl(&self) -> &DdrIfCtrl
0x200 - DDR interface Control Register
sourcepub fn ch0_wr_start_addr(&self) -> &Ch0WrStartAddr
pub fn ch0_wr_start_addr(&self) -> &Ch0WrStartAddr
0x20c - Channel 0 Write Start Address
sourcepub fn ch0_wr_end_addr(&self) -> &Ch0WrEndAddr
pub fn ch0_wr_end_addr(&self) -> &Ch0WrEndAddr
0x210 - Channel 0 Write End Address
sourcepub fn ch0_rd_start_addr(&self) -> &Ch0RdStartAddr
pub fn ch0_rd_start_addr(&self) -> &Ch0RdStartAddr
0x214 - Channel 0 Read Start Address
sourcepub fn ch0_rd_end_addr(&self) -> &Ch0RdEndAddr
pub fn ch0_rd_end_addr(&self) -> &Ch0RdEndAddr
0x218 - Channel 0 Read End Address
sourcepub fn ch1_wr_start_addr(&self) -> &Ch1WrStartAddr
pub fn ch1_wr_start_addr(&self) -> &Ch1WrStartAddr
0x224 - Channel 1 Write Start Address
sourcepub fn ch1_wr_end_addr(&self) -> &Ch1WrEndAddr
pub fn ch1_wr_end_addr(&self) -> &Ch1WrEndAddr
0x228 - Channel 1 Write End Address
sourcepub fn ch1_rd_start_addr(&self) -> &Ch1RdStartAddr
pub fn ch1_rd_start_addr(&self) -> &Ch1RdStartAddr
0x22c - Channel 1 Read Start Address
sourcepub fn ch1_rd_end_addr(&self) -> &Ch1RdEndAddr
pub fn ch1_rd_end_addr(&self) -> &Ch1RdEndAddr
0x230 - Channel 1 Read End Address
sourcepub fn ch0_ddr_fifo0_addr(&self) -> &Ch0DdrFifo0Addr
pub fn ch0_ddr_fifo0_addr(&self) -> &Ch0DdrFifo0Addr
0x240 - DDR Channel 0 Controller Interface Address FIFO0
sourcepub fn ch0_ddr_fifo1_addr(&self) -> &Ch0DdrFifo1Addr
pub fn ch0_ddr_fifo1_addr(&self) -> &Ch0DdrFifo1Addr
0x248 - DDR Channel 0 Controller Interface Address FIFO1
sourcepub fn ch0_ddr_fifo2_addr(&self) -> &Ch0DdrFifo2Addr
pub fn ch0_ddr_fifo2_addr(&self) -> &Ch0DdrFifo2Addr
0x250 - DDR Channel 0 Controller Interface Address FIFO2
sourcepub fn ch0_ddr_fifo3_addr(&self) -> &Ch0DdrFifo3Addr
pub fn ch0_ddr_fifo3_addr(&self) -> &Ch0DdrFifo3Addr
0x258 - DDR Channel 0 Controller Interface Address FIFO3
sourcepub fn ch1_ddr_fifo0_addr(&self) -> &Ch1DdrFifo0Addr
pub fn ch1_ddr_fifo0_addr(&self) -> &Ch1DdrFifo0Addr
0x260 - DDR Channel 1 Controller Interface Address FIFO0
sourcepub fn ch1_ddr_fifo1_addr(&self) -> &Ch1DdrFifo1Addr
pub fn ch1_ddr_fifo1_addr(&self) -> &Ch1DdrFifo1Addr
0x268 - DDR Channel 1 Controller Interface Address FIFO1
sourcepub fn ch1_ddr_fifo2_addr(&self) -> &Ch1DdrFifo2Addr
pub fn ch1_ddr_fifo2_addr(&self) -> &Ch1DdrFifo2Addr
0x270 - DDR Channel 1 Controller Interface Address FIFO2
sourcepub fn ch1_ddr_fifo3_addr(&self) -> &Ch1DdrFifo3Addr
pub fn ch1_ddr_fifo3_addr(&self) -> &Ch1DdrFifo3Addr
0x278 - DDR Channel 1 Controller Interface Address FIFO3