Module yaxpeax_x86::real_mode::register_class[][src]

Expand description

high-level register classes in an x86 machine, such as “2-byte general purpose”, “xmm”, “x87”, and so on. constants in this module are useful for inspecting the register class of a decoded instruction. as an example:

use yaxpeax_x86::real_mode::{self as amd64};
use yaxpeax_x86::real_mode::{Opcode, Operand, RegisterClass};
use yaxpeax_arch::{Decoder, U8Reader};

let movsx_ax_cl = &[0x0f, 0xbe, 0xc1];
let decoder = amd64::InstDecoder::default();
let instruction = decoder
    .decode(&mut U8Reader::new(movsx_ax_cl))
    .expect("can decode");

assert_eq!(instruction.opcode(), Opcode::MOVSX);

fn show_register_class_info(regclass: RegisterClass) {
    match regclass {
        amd64::register_class::W => {
            println!("  and is a word register");
        }
        amd64::register_class::B => {
            println!("  and is a byte register");
        }
        other => {
            panic!("unexpected and invalid register class {:?}", other);
        }
    }
}

if let Operand::Register(regspec) = instruction.operand(0) {
    println!("first operand is {}", regspec);
    show_register_class_info(regspec.class());
}

if let Operand::Register(regspec) = instruction.operand(1) {
    println!("first operand is {}", regspec);
    show_register_class_info(regspec.class());
}

this is preferable to alternatives like checking register names against a known list: a register class is one byte and “is qword general-purpose” can then be a simple one-byte compare, instead of 16 string compares.

yaxpeax-x86 does not attempt to further distinguish between, for example, register suitability as operands. as an example, cl is only a byte register, with no additional register class to describe its use as an implicit shift operand.

Constants

byte registers: al, cl, dl, bl, ah, ch, dh, bh.

control registers cr0 through cr7.

doubleword registers: eax through edi.

debug registers dr0 through dr7.

the full cpu flags register.

the full instruction pointer register.

AVX512 mask registers k0 through k7.

mmx registers mm0 through mm7.

segment registers es, cs, ss, ds, fs, gs.

x87 floating point stack entries st(0) through st(7).

word registers: ax through di.

xmm registers xmm0 through xmm31.

ymm registers ymm0 through ymm31.

zmm registers zmm0 through zmm31.